Vhdl Implementation Of Ds Ss-cdma Transmitter And Receiver For AD Hoc Network

In past few years, lot of research is performed in both industries and academics into the development of CDMA. In DS-SS CDMA multiple signal channels occupy the same frequency band being distinguished by the use of different spreading codes. Digital cellular telephone system and personal communication system uses CDMA communication. In this project direct sequence spread spectrum principle based code division multiple access (CDMA) transmitter and receiver is implemented in VHDL for FPGA. The transmitter module mainly consists of data generator, programmable chip sequence generator (PN sequence generator), direct digital frequency synthesizer (DDFS), BPSK modulator blocks. The receiver modular mainly consists of BPSK demodulator, programmable chip sequence generator (PN sequence generator), matched filters, threshold detector blocks. Modelsim Altera 13.1 tool will be used for functional and logic verification at each block. The Xilinx synthesis technology of Xilinx ISE 9.2i tool will be used for synthesis of transmitter and receiver on FPGA Spartan 3E. A transmitter and Receiver components have been designed individually using Bottom-up approach. The designs then are combined and defined by component declaration and port mapping. This project concentrates on application of VHDL simulation and FPGA compiler to Wireless Data components.