Switch-Level Modeling of MOS Digital Circuits

The switch-level model describes the logical behavior of digital circuits implemented in metal oxide semiconductor (MOS) technology. In this model a network consists of a set of nodes connected by transistor "switches" with each node having a state 0, 1, or X, and each transistor having a state open, closed, or unknown. The logic simulator MOSSIM II has been implemented with this model as its basis. MOSSIM II can simulate a wide variety of MOS circuits at speeds approaching those of event-driven logic gate simulators. The simulator can apply additional tests to detect potential timing errors, unrestored logic levels in CMOS, and unrefreshed dynamic charge. This paper provides an overview of the switch-level model and how it is applied in MOSSIM II