The General Interconnect Problem of Integrated Circuits

This thesis is concerned with the interconnection problem of custom integrated circuits. It may be broadly defined as the transformation of circuit description represented by the notion of modules together with the circuit connectivity requirements, into wiring patterns which implement the required connectivities. Conventional approaches to its solution are presented. Issues such as partition to placement and routing and various layout optimization tradeoffs are discussed. A detail hierarchical routing model with timing considerations that extends naturally to multiple conducting layer environment is presented. Several of the implications of this extension are also discussed. The rest of this thesis deals with an experiment with the stepping approach to routing as an alternative to the conventional cellular approach empahasing simplicity rather than optimization. Algorithms for routing signals and power developed for the stepping router are presented. An implementation of this approach by the author together with some test examples and their results are also described, This thesis concludes with a few suggestions for further research work in this area which the author considers very important from the experience gained during the work on this thesis