CUHK electronic theses & dissertations collection

As a proof of concept, the presented power-efficient design methodology is experimentally verified on a H.264/AVC baseline decoding system. A prototype chip is fabricated in UMC 0.18mum 1P6M standard CMOS technology. It is capable to decode H.264/AVC baseline profile of QCIF at 30fps. The chip contains 169k gates and 2.5k bytes on-chip SRAM with 4.5mmx4.5mm chip area. It dissipates 293muW at 1.0V and 973muW at 1.8V during realtime video decoding. Compared with conventional designs, the measured power consumption is reduced up to one order of magnitude.CMOS technology has now entered "power-limited scaling regime", where power consumption moves from being one of many design metrics to being the number one design metric. However, rapid advances of multimedia entertainment pose more stringent constraints on power dissipation mainly due to the increased video quality. Although general power-efficient design techniques have been formed for several years, no literature studied how to systematically apply them on a specific application like video decoding. Besides these general methods, video decoding has its unique power optimization entries due to temporal, spatial, and statistical redundancy in digital video data.This research focuses on a systematic way to exploit power saving potentials spanning all design levels for real-time video decoding. At the algorithm level, the computational complexity and data width are optimized. At the architectural level, pipelining and parallelism are widely adopted to reduce the operating frequency; distributed processing greatly helps to reduce the number of global communications; hierarchical memory organization moves great part of data access from larger or external memories to smaller ones. At the circuit level, resource sharing reduces total switching capacitance by multi-function reconfigurations; the knowledge about signal statistics is exploited to reduce the number of transitions; data dependent signal-gating and clock-gating are introduced which are dynamic techniques to for power reduction; multiplications, which account for large chip area and switching power, are reduced to minimum through proper transformations, while complex dividers are totally eliminated. At the transistor and physical design level, cell sizing and layout are optimized for power-efficiency purpose. The higher levels, like algorithm and architecture, contribute to larger portion of power reduction, while the lower levels, like transistor and physical, further reduce power where high level techniques are not applicable.Xu, Ke."September 2007."Adviser: Chui-Sing Choy.Source: Dissertation Abstracts International, Volume: 69-08, Section: B, page: 4952.Thesis (Ph.D.)--Chinese University of Hong Kong, 2007.Includes bibliographical references (p. 239-247).Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.Abstracts in English and Chinese.School code: 1307