A PC/AT-based ICT image archiving system.

by Ringo Wai-kit Lam.Thesis (M.Phil.)--Chinese University of Hong Kong, 1991.Includes bibliographical references.ACKNOWLEDGEMENTSABSTRACTLIST OF FIGURES --- p.iLIST OF TABLES --- p.iiiChapter CHAPTER 1 --- INTRODUCTION --- p.1-1Chapter 1.1 --- Introduction --- p.1-1Chapter 1.2 --- Transform Coding Theory --- p.1-2Chapter 1.2.1 --- Image Transform Coder and Decoder --- p.1-2Chapter 1.2.2 --- Transformation --- p.1-4Chapter 1.2.3 --- Bit Allocation --- p.1-5Chapter 1.2.4 --- Quantization --- p.1-7Chapter 1.2.5 --- Entropy Coding --- p.1-8Chapter 1.2.6 --- Error of Transform Coding --- p.1-9Chapter 1.3 --- Organization of The Thesis --- p.1-10Chapter CHAPTER 2 --- 2D INTEGER COSINE TRANSFORM CHIP SET --- p.2-1Chapter 2.1 --- Introduction --- p.2-1Chapter 2.2 --- The Integer Cosine Transform (ICT) --- p.2-2Chapter 2.3 --- LSI Implementation --- p.2-4Chapter 2.3.1 --- ICT Chip --- p.2-4Chapter 2.3.2 --- Data Sequencer --- p.2-7Chapter 2.4 --- Design Considerations --- p.2-8Chapter 2.4.1 --- ICT chip --- p.2-9Chapter 2.4.1.1 --- Specifications --- p.2-9Chapter 2.4.1.2 --- I/O Bit Length Consideration --- p.2-10Chapter 2.4.1.3 --- Selection of The Transform Matrix --- p.2-12Chapter 2.4.2 --- Data Sequencer --- p.2-16Chapter 2.4.2.1 --- Normal Operation --- p.2-16Chapter 2.4.2.2 --- Low-pass Filtering Operation --- p.2-16Chapter 2.4.2.3 --- Subsampling Operation --- p.2-17Chapter 2.5 --- Architecture --- p.2-18Chapter 2.5.1 --- ICT chip --- p.2-18Chapter 2.5.1.1 --- Input Stage --- p.2-18Chapter 2.5.1.2 --- Control Block --- p.2-19Chapter 2.5.1.3 --- Multiplier --- p.2-19Chapter 2.5.1.4 --- Accumulator --- p.2-20Chapter 2.5.1.5 --- Output Stage --- p.2-21Chapter 2.5.2 --- Data Sequencer --- p.2-21Chapter 2.5.2.1 --- Input Stage --- p.2-22Chapter 2.5.2.2 --- Control Logic --- p.2-22Chapter 2.5.2.3 --- Internal Storage --- p.2-23Chapter 2.5.2.4 --- Output Stage --- p.2-24Chapter 2.6 --- 2D Integer Cosine Transform System --- p.2-24Chapter 2.6.1 --- Hardware Architecture --- p.2-24Chapter 2.6.2 --- Timing --- p.2-26Chapter 2.7 --- Conclusion --- p.2-27Chapter CHAPTER 3 --- A PC/AT-BASED IMAGE ARCHIVING SYSTEM --- p.3-1Chapter 3.1 --- Introduction --- p.3-1Chapter 3.2 --- Design Consideration --- p.3-1Chapter 3.2.1 --- Specifications --- p.3-2Chapter 3.2.1.1 --- Operations Supported --- p.3-2Chapter 3.2.1.2 --- Image Formats --- p.3-3Chapter 3.2.1.3 --- Software --- p.3-6Chapter 3.2.2 --- Storage Format of the Coded Image --- p.3-6Chapter 3.3 --- Hardware Architecture --- p.3-8Chapter 3.3.1 --- Input Stage --- p.3-11Chapter 3.3.2 --- Inverse Transform Address Generator --- p.3-11Chapter 3.3.3 --- Input Memory --- p.3-13Chapter 3.3.3.1 --- Address Map --- p.3-14Chapter 3.3.3.2 --- Bit Map --- p.3-14Chapter 3.3.3.3 --- Class Map --- p.3-15Chapter 3.3.4 --- ICT Processor --- p.3-15Chapter 3.3.5 --- Output Memory --- p.3-16Chapter 3.3.6 --- Address Generator --- p.3-16Chapter 3.3.6.1 --- Address Generator 1 (AG1) --- p.3-17Chapter 3.3.6.2 --- Address Generator 2 (AG2) --- p.3-21Chapter 3.3.6.3 --- Address Generator 3 (AG3) --- p.3-22Chapter 3.3.7 --- Control Register --- p.3-22Chapter 3.3.8 --- Interface Consideration --- p.3-23Chapter 3.3.9 --- Frame Buffer --- p.3-23Chapter 3.4 --- Software Structure --- p.3-23Chapter 3.4.1 --- Main Menu --- p.3-24Chapter 3.4.2 --- Forward Transform --- p.3-25Chapter 3.4.3 --- Inverse Transform --- p.3-25Chapter 3.4.3.1 --- Normal --- p.3-26Chapter 3.4.3.2 --- Subsampling --- p.3-26Chapter 3.4.3.3 --- Filtering --- p.3-26Chapter 3.4.3.4 --- Album --- p.3-27Chapter 3.4.3.5 --- Display and System --- p.3-28Chapter 3.5 --- Conclusion --- p.3-29Chapter CHAPTER 4 --- SYSTEM PERFORMANCE EVALUATION --- p.4-1Chapter 4.1 --- Introduction --- p.4-1Chapter 4.2 --- Result of Image Display --- p.4-1Chapter 4.3 --- Computation Time Requirement --- p.4-12Chapter 4.4 --- Comparison to Other Transform Chips and Image Transform Systems --- p.4-16Chapter 4.5 --- Conclusion --- p.4-20Chapter CHAPTER 5 --- CONCLUSION --- p.5-1Chapter 5.1 --- Further Development --- p.5-1Chapter 5.1.1 --- Employment of JPEG Scheme --- p.5-1Chapter 5.1.2 --- ICT Chip Set --- p.5-5Chapter 5.2 --- Summary of the Image Archiving System --- p.5-6Chapter CHAPTER 6 --- REFERENCES --- p.6-1Chapter CHAPTER 7 --- APPENDIX --- p.7-