An IF-sampling switched capacitor complex lowpass sigma delta modulator with high image rejection.

by Cheng Wang-tung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 97-99).Abstracts in English and Chinese.Abstract --- p.i摘要 --- p.iAcknowledgements --- p.iiTable of Contents --- p.iiiList of Figures --- p.viiList of Tables --- p.xiChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivations --- p.1Chapter 1.2 --- Objective --- p.4Chapter 1.3 --- Outline --- p.4Chapter Chapter 2 --- Quadrature ΣΔ Modulator for A/D Conversion --- p.5Chapter 2.1 --- Introduction --- p.5Chapter 2.2 --- Oversampling ΣΔ Converter --- p.6Chapter 2.3 --- Theory of ΣΔ modulation --- p.6Chapter 2.3.1 --- Quantization noise --- p.7Chapter 2.3.2 --- Oversampling --- p.8Chapter 2.3.3 --- Noise Shaping --- p.9Chapter 2.3.4 --- Performance Parameter --- p.11Chapter 2.3.5 --- Circuit Design of ΣΔ modulator --- p.11Chapter 2.3.6 --- Case Study --- p.12Chapter 2.3.6.1 --- Transfer Function --- p.12Chapter 2.3.6.2 --- Noise Analysis of First Order ΣΔ Modulator --- p.13Chapter 2.3.6.3 --- Circuit Level Implementation: --- p.14Chapter 2.4 --- Choice of Architecture: Lowpass or Bandpass? --- p.15Chapter 2.5 --- I/Q Modulation and Image Rejection --- p.18Chapter 2.5.1 --- Quadrature signal --- p.18Chapter 2.5.2 --- I/Q Modulation --- p.19Chapter 2.6 --- Image Rejection in SC ΣΔ Complex Topology --- p.21Chapter 2.6.1 --- High Level Simulation --- p.23Chapter 2.6.2 --- Discussion --- p.26Chapter 2.7 --- Summary --- p.27Chapter Chapter 3 --- Capacitor Sharing Architecture --- p.28Chapter 3.1 --- Introduction --- p.28Chapter 3.2 --- Proposed mismatch free SC complex ΣΔ Modulator --- p.28Chapter 3.2.1 --- Principle of Operation --- p.30Chapter 3.3 --- Justification of the Proposed Idea --- p.35Chapter 3.4 --- Summary --- p.37Chapter Chapter 4 --- Transistor Level Circuit Design --- p.39Chapter 4.1 --- Introduction --- p.39Chapter 4.2 --- Design of ΣΔ Modulator --- p.39Chapter 4.2.1 --- Specification of ΣΔ Modulator --- p.40Chapter 4.3 --- Design of Operational Amplifier --- p.45Chapter 4.3.1 --- Folded-cascode Operational Amplifier --- p.45Chapter 4.3.2 --- Common Mode feedback --- p.47Chapter 4.3.3 --- Bias Circuit --- p.49Chapter 4.3.4 --- Simulation Results --- p.50Chapter 4.4 --- Design of Comparator --- p.54Chapter 4.4.1 --- Regenerative Feedback Comparator --- p.54Chapter 4.4.2 --- Simulation Results --- p.55Chapter 4.5 --- Design of Clock Generator --- p.56Chapter 4.5.1 --- Non-Overlapping clock generation --- p.57Chapter 4.5.2 --- Simulation Results --- p.58Chapter 4.6 --- Simulation Results of ΣΔ Modulator --- p.59Chapter 4.7 --- Simulation Results --- p.61Chapter 4.7.1 --- Proposed Architecture --- p.62Chapter 4.7.2 --- Traditional Architecture --- p.62Chapter 4.8 --- Summary --- p.63Chapter Chapter 5 --- Layout Considerations and Post-Layout Simulation --- p.65Chapter 5.1 --- Introduction --- p.65Chapter 5.2 --- Common-Centroid Structure --- p.65Chapter 5.3 --- Shielding Technique --- p.67Chapter 5.3.1 --- Shielding of device by substrate --- p.67Chapter 5.3.2 --- Floor Planning --- p.68Chapter 5.4 --- Layout of Power Rail --- p.69Chapter 5.5 --- Layout and Post-Layout Simulation of OpAmp --- p.70Chapter 5.6 --- Layout and Post-Layout Simulation --- p.74Chapter 5.6.1 --- Proposed Architecture --- p.75Chapter 5.6.2 --- Traditional Architecture --- p.77Chapter 5.7 --- Summary --- p.79Chapter Chapter 6 --- Measurement Results --- p.81Chapter 6.1 --- Introduction --- p.81Chapter 6.2 --- Considerations of PCB Design --- p.82Chapter 6.3 --- Measurement Setup --- p.83Chapter 6.4 --- Measurement Results --- p.85Chapter 6.4.1 --- Measurement Results of Proposed Architecture --- p.85Chapter 6.5 --- Summary --- p.92Chapter Chapter 7 --- Conclusion --- p.95Chapter 7.1 --- Conclusion --- p.95Chapter 7.2 --- Future Works --- p.96References --- p.97Appendix --- p.100Chapter A.1 --- Publications --- p.100Chapter A.2 --- Schematic of proposed front end --- p.101Chapter A.3 --- Schematic of SC ΣΔ modulator --- p.102Chapter A.4 --- Schematic of the folded-cascode amplifier --- p.103Chapter A.5 --- Schematic of biasing circuit --- p.104Chapter A.6 --- Schematic of preamplifier in comparator --- p.105Chapter A.7 --- Schematic of latched part in comparator --- p.106Chapter A.8 --- Schematic of the clock generator --- p.10