Asynchronous memory design.

by Vincent Wing-Yun Sit.Thesis submitted in: June 1997.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references (leaves 1-4 (3rd gp.)).Abstract also in Chinese.TABLE OF CONTENTSLIST OF FIGURESLIST OF TABLESACKNOWLEDGEMENTSABSTRACTChapter 1. --- INTRODUCTION --- p.1Chapter 1.1 --- ASYNCHRONOUS DESIGN --- p.2Chapter 1.1.1 --- POTENTIAL ADVANTAGES --- p.2Chapter 1.1.2 --- DESIGN METHODOLOGIES --- p.2Chapter 1.1.3 --- SYSTEM CHARACTERISTICS --- p.3Chapter 1.2 --- ASYNCHRONOUS MEMORY --- p.5Chapter 1.2.1 --- MOTIVATION --- p.5Chapter 1.2.2 --- DEFINITION --- p.9Chapter 1.3 --- PROPOSED MEMORY DESIGN --- p.10Chapter 1.3.1 --- CONTROL INTERFACE --- p.10Chapter 1.3.2 --- OVERVIEW --- p.11Chapter 1.3.3 --- HANDSHAKE CONTROL PROTOCOL --- p.13Chapter 2. --- THEORY --- p.16Chapter 2.1 --- VARIABLE BIT LINE LOAD --- p.17Chapter 2.1.1 --- DEFINITION --- p.17Chapter 2.1.2 --- ADVANTAGE --- p.17Chapter 2.2 --- CURRENT SENSING COMPLETION DETECTION --- p.18Chapter 2.2.1 --- BLOCK DIAGRAM --- p.19Chapter 2.2.2 --- GENERAL LSD CURRENT SENSOR --- p.21Chapter 2.2.3 --- CMOS LSD CURRENT SENSOR --- p.23Chapter 2.3 --- VOLTAGE SENSING COMPLETION DETECTION --- p.28Chapter 2.3.1 --- DATA READING IN MEMORY CIRCUIT --- p.29Chapter 2.3.2 --- BLOCK DIAGRAM --- p.30Chapter 2.4 --- MULTIPLE DELAYS COMPLETION GENERATION --- p.32Chapter 2.4.1 --- ADVANTAGE --- p.32Chapter 2.4.2 --- BLOCK DIAGRAM --- p.33Chapter 3. --- IMPLEMENTATION --- p.35Chapter 3.1 --- 1M-BIT SRAM FRAMEWORK --- p.36Chapter 3.1.1 --- INTRODUCTION --- p.36Chapter 3.1.2 --- FRAMEWORK --- p.36Chapter 3.2 --- CONTROL CIRCUIT --- p.40Chapter 3.2.1 --- CONTROL SIGNALS --- p.40Chapter 3.2.1.1 --- EXTERNAL CONTROL SIGNALS --- p.40Chapter 3.2.1.2 --- INTERNAL CONTROL SIGNALS --- p.41Chapter 3.2.2 --- READ / WRITE STATE TRANSITION GRAPHS --- p.42Chapter 3.2.3 --- IMPLEMENTATION --- p.43Chapter 3.3 --- BIT LINE SEGMENTATION --- p.45Chapter 3.3.1 --- FOUR REGIONS SEGMENTATION --- p.46Chapter 3.3.2 --- OPERATION --- p.50Chapter 3.3.3 --- MEMORY CELL --- p.51Chapter 3.4 --- CURRENT SENSING COMPLETION DETECTION --- p.52Chapter 3.4.1 --- ONE BIT DATA BUS --- p.53Chapter 3.4.2 --- EIGHT BITS DATA BUS --- p.55Chapter 3.5 --- VOLTAGE SENSING COMPLETION DETECTION --- p.57Chapter 3.5.1 --- ONE BIT DATA BUS --- p.57Chapter 3.5.2 --- EIGHT BITS DATA BUS --- p.59Chapter 3.6 --- MULTIPLE DELAYS COMPLETION GENERATION --- p.60Chapter 4. --- SIMULATION --- p.63Chapter 4.1 --- SIMULATION ENVIRONMENT --- p.64Chapter 4.1.1 --- SIMULATION PARAMETERS --- p.64Chapter 4.1.2 --- MEMORY TIMING SPECIFICATIONS --- p.64Chapter 4.1.3 --- BIT LINE LOAD DETERMINATION --- p.67Chapter 4.2 --- BENCHMARK SIMULATION --- p.69Chapter 4.2.1 --- CIRCUIT SCHEMATIC --- p.69Chapter 4.2.2 --- RESULTS --- p.71Chapter 4.3 --- CURRENT SENSING COMPLETION DETECTION --- p.73Chapter 4.3.1 --- CIRCUIT SCHEMATIC --- p.73Chapter 4.3.2 --- SENSE AMPLIFIER CURRENT CHARACTERISTICS --- p.75Chapter 4.3.3 --- RESULTS --- p.76Chapter 4.3.4 --- OBSERVATIONS --- p.80Chapter 4.4 --- VOLTAGE SENSING COMPLETION DETECTION --- p.82Chapter 4.4.1 --- CIRCUIT SCHEMATIC --- p.82Chapter 4.4.2 --- RESULTS --- p.83Chapter 4.5 --- MULTIPLE DELAYS COMPLETION GENERATION --- p.89Chapter 4.5.1 --- CIRCUIT SCHEMATIC --- p.89Chapter 4.5.2 --- RESULTS --- p.90Chapter 5. --- TESTING --- p.97Chapter 5.1 --- TEST CHIP DESIGN --- p.98Chapter 5.1.1 --- BLOCK DIAGRAM --- p.98Chapter 5.1.2 --- SCHEMATIC --- p.100Chapter 5.1.3 --- LAYOUT --- p.102Chapter 5.2 --- HSPICE POST-LAYOUT SIMULATION RESULTS --- p.104Chapter 5.2.1 --- GRAPHICAL RESULTS --- p.105Chapter 5.2.2 --- VOLTAGE SENSING COMPLETION DETECTION --- p.108Chapter 5.2.3 --- MULTIPLE DELAYS COMPLETION GENERATION --- p.114Chapter 5.3 --- MEASUREMENTS --- p.117Chapter 5.3.1 --- LOGIC RESULTS --- p.118Chapter 5.3.1.1 --- METHOD --- p.118Chapter 5.3.1.2 --- RESULTS --- p.118Chapter 5.3.2 --- TIMING RESULTS --- p.119Chapter 5.3.2.1 --- METHOD --- p.119Chapter 5.3.2.2 --- GRAPHICAL RESULTS --- p.121Chapter 5.3.2.3 --- VOLTAGE SENSING COMPLETION DETECTION --- p.123Chapter 5.3.2.4 --- MULTIPLE DELAYS COMPLETION GENERATION --- p.125Chapter 6. --- DISCUSSION --- p.127Chapter 6.1 --- CURRENT SENSING COMPLETION DETECTION --- p.128Chapter 6.1.1 --- COMMENTS AND CONCLUSION --- p.128Chapter 6.1.2 --- SUGGESTION --- p.128Chapter 6.2 --- VOLTAGE SENSING COMPLETION DETECTION --- p.129Chapter 6.2.1 --- RESULTS COMPARISON --- p.129Chapter 6.2.1.1 --- GENERAL --- p.129Chapter 6.2.1.2 --- BIT LINE LOAD --- p.132Chapter 6.2.1.3 --- BIT LINE SEGMENTATION --- p.133Chapter 6.2.2 --- RESOURCE CONSUMPTION --- p.133Chapter 6.2.2.1 --- AREA --- p.133Chapter 6.2.2.2 --- POWER --- p.134Chapter 6.2.3 --- COMMENTS AND CONCLUSION --- p.134Chapter 6.3 --- MULTIPLE DELAY COMPLETION GENERATION --- p.135Chapter 6.3.1 --- RESULTS COMPARISON --- p.135Chapter 6.3.1.1 --- GENERAL --- p.135Chapter 6.3.1.2 --- BIT LINE LOAD --- p.136Chapter 6.3.1.3 --- BIT LINE SEGMENTATION --- p.137Chapter 6.3.2 --- RESOURCE CONSUMPTION --- p.138Chapter 6.3.2.1 --- AREA --- p.138Chapter 6.3.2.2 --- POWER --- p.138Chapter 6.3.3 --- COMMENTS AND CONCLUSION --- p.138Chapter 6.4 --- GENERAL COMMENTS --- p.139Chapter 6.4.1 --- COMPARISON OF THE THREE TECHNIQUES --- p.139Chapter 6.4.2 --- BIT LINE SEGMENTATION --- p.141Chapter 6.5 --- APPLICATION --- p.142Chapter 6.6 --- FURTHER DEVELOPMENTS --- p.144Chapter 6.6.1 --- INTERACE WITH TWO-PHASE HCP --- p.144Chapter 6.6.2 --- DATA BUS EXPANSION --- p.146Chapter 6.6.3 --- SPEED OPTIMIZATION --- p.147Chapter 6.6.4 --- MODIFIED WRITE COMPLETION METHOD --- p.150Chapter 7. --- CONCLUSION --- p.152Chapter 7.1 --- PROBLEM DEFINITION --- p.152Chapter 7.2 --- IMPLEMENTATION --- p.152Chapter 7.3 --- EVALUATION --- p.153Chapter 7.4 --- COMMENTS AND SUGGESTIONS --- p.155Chapter 8. --- REFERENCES --- p.R-lChapter 9. --- APPENDIX --- p.A-lChapter 9.1 --- HSPICE SIMULATION PARAMETERS --- p.A-lChapter 9.1.1 --- TYPICAL SIMULATION CONDITION --- p.A-lChapter 9.1.2 --- FAST SIMULATION CONDITION --- p.A-3Chapter 9.1.3 --- SLOW SIMULATION CONDITION --- p.A-4Chapter 9.2 --- SRAM CELL LAYOUT AND NETLIST --- p.A-5Chapter 9.3 --- TEST CHIP SPECIFICATIONS --- p.A-8Chapter 9.3.1 --- GENERAL SPECIFICATIONS --- p.A-8Chapter 9.3.2 --- PIN ASSIGNMENT --- p.A-9Chapter 9.3.3 --- TIMING DIAGRAMS AND SPECIFICATIONS --- p.A-10Chapter 9.3.4 --- SCHEMATICS AND LAYOUTS --- p.A-11Chapter 9.3.4.1 --- STANDARD MEMORY COMPONENTS --- p.A-12Chapter 9.3.4.2 --- DVSCD AND MDCG COMPONENTS --- p.A-20Chapter 9.3.5 --- MICROPHOTOGRAPH --- p.A-2