An asynchronous forth microprocessor.

Ping-Ki Tsang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2000.Includes bibliographical references (leaves 87-95).Abstracts in English and Chinese.Abstract --- p.iAcknowledgments --- p.iiiChapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation and Aims --- p.1Chapter 1.2 --- Contributions --- p.3Chapter 1.3 --- Overview of the Thesis --- p.4Chapter 2 --- Asynchronous Logic g --- p.6Chapter 2.1 --- Motivation --- p.6Chapter 2.2 --- Timing Models --- p.9Chapter 2.2.1 --- Fundamental-Mode Model --- p.9Chapter 2.2.2 --- Delay-Insensitive Model --- p.10Chapter 2.2.3 --- QDI and Speed-Independent Models --- p.11Chapter 2.3 --- Asynchronous Signalling Protocols --- p.12Chapter 2.3.1 --- 2-phase Handshaking Protocol --- p.12Chapter 2.3.2 --- 4-phase Handshaking Protocol --- p.13Chapter 2.4 --- Data Representations --- p.14Chapter 2.4.1 --- Dual Rail Coded Data --- p.15Chapter 2.4.2 --- Bundled Data --- p.15Chapter 2.5 --- Previous Asynchronous Processors --- p.16Chapter 2.6 --- Summary --- p.20Chapter 3 --- The MSL16 Architecture --- p.21Chapter 3.1 --- RISC Machines --- p.21Chapter 3.2 --- Stack Machines --- p.23Chapter 3.3 --- Forth and its Applications --- p.24Chapter 3.4 --- MSL16 --- p.26Chapter 3.4.1 --- Architecture --- p.28Chapter 3.4.2 --- Instruction Set --- p.30Chapter 3.4.3 --- The Datapath --- p.32Chapter 3.4.4 --- Interrupts and Exceptions --- p.33Chapter 3.4.5 --- Implementing Forth primitives --- p.34Chapter 3.4.6 --- Code Density Estimation --- p.34Chapter 3.5 --- Summary --- p.35Chapter 4 --- Design Methodology --- p.37Chapter 4.1 --- Basic Notation --- p.38Chapter 4.2 --- Specification of MSL16A --- p.39Chapter 4.3 --- Decomposition into Concurrent Processes --- p.41Chapter 4.4 --- Separation of Control and Datapath --- p.45Chapter 4.5 --- Handshaking Expansion --- p.45Chapter 4.5.1 --- 4-Phase Handshaking Protocol --- p.46Chapter 4.6 --- Production-rule Expansion --- p.47Chapter 4.7 --- Summary --- p.48Chapter 5 --- Implementation --- p.49Chapter 5.1 --- C-element --- p.49Chapter 5.2 --- Mutual Exclusion Elements --- p.51Chapter 5.3 --- Caltech Asynchronous Synthesis Tools --- p.53Chapter 5.4 --- Stack Design --- p.54Chapter 5.4.1 --- Eager Stack Control --- p.55Chapter 5.4.2 --- Lazy Stack Control --- p.56Chapter 5.4.3 --- Eager/Lazy Stack Datapath --- p.53Chapter 5.4.4 --- Pointer Stack Control --- p.61Chapter 5.4.5 --- Pointer Stack Datapath --- p.62Chapter 5.5 --- ALU Design --- p.62Chapter 5.5.1 --- The Addition Operation --- p.63Chapter 5.5.2 --- Zero-Checker --- p.64Chapter 5.6 --- Memory Interface and Tri-state Buffers --- p.64Chapter 5.7 --- MSL16A --- p.65Chapter 5.8 --- Summary --- p.66Chapter 6 --- Results --- p.67Chapter 6.1 --- FPGA based implementation of MSL16 --- p.67Chapter 6.2 --- MSL16A --- p.69Chapter 6.2.1 --- A Comparison of 3 Stack Designs --- p.69Chapter 6.2.2 --- Evaluation of the ALU --- p.73Chapter 6.2.3 --- Evaluation of MSL16A --- p.74Chapter 6.3 --- Summary --- p.81Chapter 7 --- Conclusions --- p.83Chapter 7.1 --- Future Work --- p.85Bibliography --- p.87Publications --- p.9