Low-power techniques for supply-noise mitigation in phase-locked\ud loops

Graduation date: 2010Modern day digital systems employ frequency\ud synthesizers to provide a common clock to the system.\ud They are undergoing large scale integration due to which, mitigation\ud of the effect of noise on power supply has become a major design consideration\ud in clocking circuits. Rapid scaling of CMOS technology mandates the\ud design of frequency synthesizers in a low supply voltage environment.\ud Maintaining the supply noise immunity of clocking circuits in low-voltage \ud processes is particularly challenging.\ud \ud In this thesis, techniques to mitigate the effect of supply-noise \ud in frequency synthesizers are\ud explored. The ring-oscillator based frequency synthesizer\ud is an important part of many clocking circuits.\ud They are used in various digital communication systems and as a \ud building block in high speed signalling systems.\ud They suffer from high sensitivity to power supply noise thereby requiring\ud careful design considerations to improve its supply noise immunity.\ud In light of the above, an attempt has been made to\ud improve the immunity of the ring-oscillator based frequency synthesizer\ud to noise on the supply voltage. The effect of noise on\ud the supplies of other building blocks of a frequency synthesizer, \ud though not as pronounced as that of noise on the ring-oscillator supply,\ud is quite significant. Analysis of effect of power supply noise on \ud various building blocks of the frequency synthesizer are presented.\ud Also, techniques to effectively reduce the effect of power supply noise\ud on the performance of the frequency synthesizer are presented.\ud Measured results from proof-of-concept ICs are presented to illustrate the\ud effectiveness of the proposed techniques.\ud \ud Clock and data recovery (CDR) circuits which utilize ring-oscillators are\ud also highly sensitive to power supply noise. Measurement of CDR jitter \ud tolerance without the use of expensive equipment is another challenge involved\ud in the design of CDRs. An on-chip jitter tolerance measurement technique is \ud presented wherein, a phase averaging dual loop CDR architecture is used\ud which comprises of a phase-locked loop (PLL) inside the CDR loop.\ud Previously proposed idea of using oversampling in this architecture has proven\ud to considerably \ud reduce power consumption in this CDR architecture. In this thesis, an \ud attempt has been made to further reduce the power consumption.\ud The PLL in this CDR architecture utilizes the proposed supply regulated PLL\ud architecture in order to minimize the bit-error rate (BER) of the CDR due to \ud power supply noise