Design of high-performance pipeline analog-to-digital converters in low-voltage processes

Graduation date: 2005Pipeline analog-to-digital converters (ADCs) have long been used in high-speed\ud systems for power-efficient data conversion. Broadband communication and video processing systems are placing high demands on converter accuracy and speed (above 14 bits\ud and in the multiple-MHz range). The increasing converter requirements coupled with\ud lower supply voltages in modern processes makes designing pipeline ADCs to meet these\ud requirements exceedingly difficult.\ud This thesis addresses the issues associated with designing a pipeline ADC for high\ud accuracy under modern low-voltage process limitations. Fundamental barriers to an\ud economical solution at this accuracy level, such as kT/C thermal noise, are addressed\ud through system and circuit level design. These include such concepts as rail-to-rail\ud inputs for improved signal power and sample-and-hold (S/H) removal for noise and\ud power savings.\ud The presented concepts are combined in a prototype design implementation using\ud a 0.18μm, 1.8V process. This serves as a platform for addressing issues with integrating\ud the ideas simultaneously. Simulations and modeling presented illustrate the feasibility\ud of such a design