Memory built in self test implementation using Mentor Graphics Tessent

With the advent of deep-submicron VLSI technology, core-based system-on-chip (SOC) design is attracting an increasing attention. On an SOC, popular reusable cores include memories (such as ROM, SRAM, DRAM and flash memory), processors (such as CPU, DSP and microcontroller), input/output circuits, etc. Memory cores are obviously among the most universal ones-almost all system chips contain some type of embedded memory. However, to provide a low cost test solution for the on-chip memory cores is not a trivial task. This report presents a study on memory BIST, algorithms of different test patterns, and discussion of some novel design issues