Fault secure encoder and decoder for NanoMemory applications

Includes bibliographical references (leaf 24)The Project is based on the study of NanoMemory structures and it introduces a new approach for the design of Memory blocks in the Digital devices where the data loss due to transient errors and other parameter changes are more. The aim of the project is to design a programmable fault secure encoder and decoder circuitry for memory design. The key contribution of this project is to identify and define a new class of error-correcting codes whose redundancy makes the design fault secure detectors (FSD) simple. Also, the fault-tolerant nanoscale memory architecture which tolerates transient faults both in storage unit and in the supporting logic (i.e. encoder decoder (corrector) and detector circuits) is introduced. It is also proven that the Euclidean Geometry Low-Density Parity-Check (EG-LDPC) codes have the fault-secure detector capability. [1] Hence we are utilizing the EG-LDPC concept to retrieve the original information from the defected memory content. The system is designed with low power logical elements; hence the power consumption is also reduced