Design and implementation of configuration modules in a programmable hardware-assisted cache emulator (PHA$E)

Graduation date: 2005Memory hierarchy design is becoming more important as the speed gap be-\ud tween processor and memory continues to grow. Investigations of memory perfor-\ud mance have typically been conducted using trace-driven emulation, which could\ud take tremendous resources (e.g. long emulation time, large storage requirements\ud for traces, and high overall cost). Recent research has proposed the use of hard-\ud ware for performing cache emulations. Such an approach is advantageous as it can\ud be done in real-time, which eliminates the need for large storage for traces, reduces\ud the emulation time, and improves the accuracy of the results. This thesis discusses\ud the preliminary work with the Programmable Hardware Assisted Cache Emulator\ud (PHA$E), a system for emulating cache in real-time. PHA$E is implemented using\ud Field Programmable Gate Array (FPGA) chips, so it is flexible and configurable.\ud Once configured, PHA$E can emulate various sizes of cache, different cache orga-\ud nizations, and many replacement algorithms. This thesis describes the design and\ud implementation of Very High Speed Integrated Circuit Hardware Description Lan-\ud guage (VHDL) modules that were programmed into PAH$E to make it capable of\ud emulating off-chip shared level 3 caches with varying sizes and set-associativities.\ud Furthermore, the emulation results from SPEC benchmarks (SPECcpu2000 and SPECjAppServer2002 [13]), and a large vocabulary continuous speech recognition\ud (LVCSR) system [24] are presented to verify the functionality of PHA$E. Lastly,\ud future research directions are identified