Low power implementation of reconfigurable parallel ALU

With technology scaling towards nanometer scale, the transistor aging and breakdown\ud effects are becoming more prominent. Such effects result in system failure, if not\ud addressed properly at the circuit and architecture level. Reconfigurable parallel\ud architectures are inherently tolerant to failures due to deployment of redundancy and\ud reconfigurability. The research goal here is to physically implement a parallel\ud reconfigurable ALU in 90 nm CMOS technology following the Application Specific\ud Integrated Circuit (ASIC) design methodology. In such architecture, the redundant units\ud can be shut down or put in low power mode. The conventional Verilog HDL does not\ud support such low power techniques to be specified at RTL level. The new emerging\ud Unified Power Format (UPF) allows specification of low power techniques at RTL. We\ud will use UPF to specify power gating design technique at RTL and then take the design\ud through ASIC design flow from RTL to GDS layout. We will also obtain power,\ud performance, and area results for validation purpose and for demonstrating the benefits\ud of such architecture