Optimization of supply voltage for mininum energy in power gated CMOS circuits

Technology scaling according to Moore???s law has resulted in the development of\ud integrated chips; it has also posed several limitations in terms of power consumption and\ud performance. Voltage scaling in particular has led to several tradeoffs. One of its\ud tradeoffs is its effect on the power consumption. As the supply voltage (Vdd) is scaled\ud down to voltage below the threshold voltage (Vt) value, the sub threshold leakage\ud current (lleak) increases and hence the static power dissipation increases. It has been\ud noticed that, due to scaling, the static power is contributing to almost 40% of the total\ud power consumption.\ud Power gating is one of the methods that can be employed in order to mitigate the risk of\ud increasing leakage current. Dynamic power gating is a technique that can be used to\ud dynamically turn the sleep transistor ON only for the time period the circuit performs the\ud computation and immediately switches to OFF when the circuit is inactive. As the sleep\ud transistor will be ON during the computation period, the leakage current is mitigated and\ud hence overall power consumption is reduced. This research is performed inorder to\ud determine an optimal value of supply voltage by performing dynamic powergating and\ud voltage scaling to design a low power circuit