Design and modeling of an analog to digital converter using FPGA board

Includes bibliographical references (pages 81-86)In this project the design and modeling of an analog to digital converter using a field programming gate array (FPGA) board is presented. The FPGA contains digital components that make it possible to implement a digital ADC. The simulation is done using Xilinx Spartan 3E board and a hardware description language VHDL is used to design and simulate different ways of implementing a Single-Slope ADC; each has its pros and cons in terms of speed and resolution. By using different parameters to implement the Single-Slope ADC, we will find out the possibility of achieving different speed and resolution of the digital ADC. \ud First the analog input signal is fed to the FPGA through low voltage differential signaling pins (LVDS) that are available in most of the FPGAs. The signal is processed and converted inside the FPGA to a digital form. The output of the FPGA is sent to a low pass filter in order to convert the signal back to analog and used as a reference voltage