Reliability analysis of power gated SRAM under combined effects of NBTI, PBTI in nano-scale CMOS

Transistor aging effects (NBTI and PBTI) impact the reliability of SRAM in Nano-scale CMOS technologies. In this research, the combined effect of NBTI and PBTI on power gated SRAM is analyzed. Optimal source biasing in the standby mode is presented as an effective method for guard-banding against the aging effects. The simulations results in a predictive 32nm technology shows maximum of 1.6% reduction in standby SNM over 5 year lifetime. For optimum operation, by decreasing the standby source bias voltage by only 0.012 volts, the SNM is safely margined for 5 year life time. This guard-banding comes at an insignificant power overhead of 0.6% for applied worse case scenarios. Given the insignificant power overhead with such guard-banding, it is concluded that adaptive tuning of the source biasing voltage is not required, given the not so negligible complexity and overhead associated with adaptive techniques. Furthermore we present a perspective for using CNTFET technology on SRAM cells, and quantify our results by comparing the performance parameters of 6T SRAM Cell between lOnm CNTFET technology and 16nm (PTM) CMOS. Our simulations results show that CNTFET based SRAM design is a viable design to choose compared to its CMOS counterpart. The results show that there is a 52.7% increase in SNM of the memory cell. Meanwhile, the cell becomes 5% faster, with a reduction in standby power by 52%. These results clearly justify that CNTFET is more suitable for circuit design rather than MOSFETs. This comparative study would definitely help us choose better technology alternatives in near future