FPGA power optimization

Includes bibliographical references (pages 42-42)FPGA power optimization has become a major part of a design on demand in today???s application specially military and aerospace. The project shows a rundown of Xilinx series 7 FPGA low-power design techniques at various stages of development cycle. In a given FPGA design power has become a primary factor. Therefore power management would be critical in most applications. Specifying maximum power per chip or system is becoming the industry standard. As such, designers have to bring power much earlier in the design flow.\ud By lowering power longer life for battery and higher reliability for the system is achieved.\ud Transistors are becoming smaller in each generation of chip technology. This phenomenon has lead to more leakage within each transistor. More leakage leads to more static power -which is, the current of the transistors when they are turned off. By increasing FPGA performance i.e. higher clock rate, the FPGA dynamic power has also increased. This project covers different techniques for SRAM based FPGA power optimization with design examples verifying the validity of the power optimization