Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS

Project (M.S., Electrical and Electronic Engineering) -- California State University, Sacramento, 2010.The aim of this project was to design, simulate and layout a charge pump for a phase locked loop (PLL) FM synthesizer in a 0.5um CMOS process. The charge pump uses Up and Down input signals provided by a phase frequency detector and converts them into output charge pulses integrated on a loop filter capacitor. According to the difference between the reference clock and the divided output of the voltage controlled oscillator (VCO), the charge pump charges or discharges the loop filter capacitor. The capacitor voltage is subsequently used to control the frequency of the VCO, thereby controlling the frequency at the output of the PLL.Electrical and Electronic Engineerin