Low voltage techniques for pipelined analog-to-digital converters

Graduation date: 2007To realize pipelined ADCs in deep-submicron processes, low voltage techniques\ud must be developed to work around problems created by limited supply voltages such as\ud the floating switch dead zone, reduced SNR, and reduced OpAmp performance.\ud This thesis analyzes standard and low voltage design issues for pipelined ADCs\ud and proposes a fully-differential implementation of the OpAmp Reset Switching\ud Technique (ORST) as a suitable low voltage design solution. The technique uses a true\ud fully differential MDAC structure with a switching common-mode feedback to achieve\ud increased linearity and noise performance over the previously published ORST.\ud A pipelined ADC test chip is designed to implement the fully differential ORST\ud technique as a proof of concept. The design also includes a simple, low power input\ud sampling network that also allows an increased input signal range and saves power by\ud removing the dedicated, front-end S/H.\ud Prototype performance demonstrates the fully differential ORST and shows\ud sampling speeds of up to 60 MS/s, 51.4 dB SNR, 58.8 dB SFDR, and 49.7 dB SNDR for\ud an 8-bit ENOB in a 0.18 μm CMOS process with a 1 V supply. Little change in distortion\ud is observed up to 90 MHz input frequency, demonstrating operation without a S/H