Floating-point Network Node for Multi-University Research Network

Floating-point operations are complex, they are both power and area intensive. The performance of floating-point operations can have a significant impact on the overall performance of a processor. This thesis explores the design, verification and testing of a synchronous pipelined out-of-order IEEE-754 compliant floating-point unit (FPU) for the Santa Cruz Out of Order RISC Engine (SCOORE).SCOORE is a superscalar out-of-order SparcV8 processor and is currently under development in the micro-architecture Santa Cruz (MASC) Laboratory. The processor is planned to be taped out in the 28nm GLOBALFOUNDRIES process as a part of the Multi UniversityResearch Network. Our FPU provides hardware support for floating-point addition, subtraction, multiplication, division, square-root arithmetic operations for single as well as double precision.The design is modeled using the Verilog-2001 HDL and implemented using the STM 90nm process.The three major design units described in this work are a traditional Flop-based pipelined FPU; a latch-based pipelined FPU utilizing the retry mechanism; and the FPU ring network node consisting of the FPU, the programmable built-in self test (BIST) and the demultiplexer (DMUX). The design achieves the operating frequency goal of 1.4 GHz on the TSMC 90nm process