Developing Through-Wafer Via (TWV) and Plasma Dicing Process for Silicon Interconnect Fabric (Si-IF)

In this thesis, the through-wafer via (TWV) technology is developed for signal and power delivery on silicon interconnect fabric (Si-IF). The electrical performance of through-wafer via is simulated by ANSYS HFSS with different design parameters. Low insertion loss is obtained when it is operating at the low-frequency range (<1GHz). The electrical reliability issues such as electromigration are examined and verified. The thermal reliability issues related to TWV during Si-IF fabrication are analyzed by simulation. It is observed that interfacial delamination can be induced at the interface between Cu via and SiO2 liner due to the CTE mismatch between the materials. The TWV is fabricated in UCLA Nanolab on a 300μm thick wafer. Plasma dicing technology is also developed based on deep silicon etch to obtain smooth die edge after dicing, which enables compact die assembly on Si-IF