A Comparative Study between RTL and HLS for Image Processing Applications with FPGAs

High-level synthesis (HLS) and register transfer level (RTL) are two popular methods to design FPGAs. Both of methods have advantages and disadvantages: HLS provides ease of development, and is less prone to error. Thus, it reduces the development time significantly when designing a hardware system. On the other hand, RTL development enables the developer to make lower level design decisions which can increase the performance and efficiency of the system. Although there have been several studies on comparing HLS and RTL in terms of cost, performance, and area for higher level applications, these studies do not make a one-on-one comparison on the micro-architectural details of a given application. In this thesis, we take further steps to compare HLS and RTL by analyzing the lower level micro-architectural details in HLS and RTL designs for the same applications. We also provide guidelines on how to create these architectures efficiently in both methods. We investigate several image processing algorithms and their designs in RTL and HLS. The algorithms were selected based on their ubiquitous nature and widespread use in image processing applications. We show that if HLS is used to its full potential, it can achieve comparable level of performance as the systems designed using RTL