Performance and Power Optimization for Multi-core Systems using Multi-level Scaling

Integrating more cores per chip to increase the performance of processors has been trendingfor the past decade. However, this trend cannot be sustained because the reduction in powerconsumption per core has slowed down while the power budget per chip has not increased.Modern processor chips are becoming so power constrained to the point that not all theirdevices can be powered at once - this is often referred to as dark silicon. To maximizeperformance within these power constraints, the system must carefully select the set ofresources to be used.To solve this problem, several power management techniques such as Dynamic Voltage/FrequencyScaling (DVFS), core scaling, and resource scaling have been the subject of active researchand have proven to be effective. However, most of these solutions are sub-optimal becausethey explore only one layer of the architecture. Although considering one layer reduces thecomplexity of the technique, it limits the exploitation of potential improvement in performanceand energy consumption.The problem is an order of magnitude more complex for power constrained multi-core architectures.We need power management systems that can take advantage of dierent scalingtechniques. Many studies have been conducted on scaling with the sole objective of performanceimprovement. Nevertheless, few of them have considered both performance and energy consumption in the optimization process.This dissertation proposes an optimization technique that balances performance and energyconsumption by applying a joint control of core, resource and frequency scaling. Thissystem finds the optimal configuration for a given application and accordingly adapts thearchitecture configuration.The proposed technique consists of three stages: configuration sampling, response surfacemodels to approximate performance and energy consumption, and online optimization usinga genetic algorithm (GA). To evaluate the system, experiments were conducted on asimulated 12 core architecture. Our experiments have shown that the performance couldimprove by 15% on average while achieving energy savings of up to 26%. Using a per-coreconfiguration improves the performance by 25% on average and reduces the energy by 18%