Add to ORKGThis report describes different strategies for area, power, and time optimization for designs on microarchitectural and logic levels as implemented in MILO system
Increasing demand for power-efficient, high-performance computing requires tuning applications and/o...
In the field of VLSI circuit optimization, the scaling of semiconductor devices has led to the minia...
The transition to multiprocessors expands the space of viable core designs and requires sophisticate...
This report describes different strategies for area, power, and time optimization for designs on mic...
In this report we discuss strengths and weaknesses of logic synthesis systems and describe a system ...
This thesis spans two levels of the design process by examining optimization at both the register-tr...
In recent years the drive to produce more complex integrated circuits while spending less design tim...
Adaptive microarchitectures are a promising solution for designing high-performance, power-efficient...
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto...
Due to the character of the original source materials and the nature of batch digitization, quality ...
In this thesis we tackle one of the most important fields of research, which is reducing power consu...
We propose a classification of high and low-level compiler optimizations to reduce the clock period,...
We propose and apply a new simulation paradigm for microarchitectural design evaluation and optimiza...
The continuing advances in VLSI technology have fueled dramatic performance gains for general-purpo...
Adaptive microarchitectures are a promising solution for designing high-performance, power-efficient...
Increasing demand for power-efficient, high-performance computing requires tuning applications and/o...
In the field of VLSI circuit optimization, the scaling of semiconductor devices has led to the minia...
The transition to multiprocessors expands the space of viable core designs and requires sophisticate...
This report describes different strategies for area, power, and time optimization for designs on mic...
In this report we discuss strengths and weaknesses of logic synthesis systems and describe a system ...
This thesis spans two levels of the design process by examining optimization at both the register-tr...
In recent years the drive to produce more complex integrated circuits while spending less design tim...
Adaptive microarchitectures are a promising solution for designing high-performance, power-efficient...
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto...
Due to the character of the original source materials and the nature of batch digitization, quality ...
In this thesis we tackle one of the most important fields of research, which is reducing power consu...
We propose a classification of high and low-level compiler optimizations to reduce the clock period,...
We propose and apply a new simulation paradigm for microarchitectural design evaluation and optimiza...
The continuing advances in VLSI technology have fueled dramatic performance gains for general-purpo...
Adaptive microarchitectures are a promising solution for designing high-performance, power-efficient...
Increasing demand for power-efficient, high-performance computing requires tuning applications and/o...
In the field of VLSI circuit optimization, the scaling of semiconductor devices has led to the minia...
The transition to multiprocessors expands the space of viable core designs and requires sophisticate...