Add to ORKGThis paper describes a method for incorporating layout parameters to better meet performance contraints. We define an algorithm for synthesis of high-performance designs and present a synthesis tool for use with custom layout generators. Experimental results indicate such an approach produces faster layouts and permits greater area/time tradeoffs than traditional logic synthesis systems
[[abstract]]As feature sizes shrink to deep sub-micron, the performance of VLSI chips becomes domina...
A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presen...
This paper presents the novel idea of multi-placement struc-tures, for a fast and optimized placemen...
This paper describes a method for incorporating layout parameters to better meet performance contrai...
International audienceThis paper presents a methodology for the synthesis of high performance analog...
As the technology advances, millions of transistors can be integrated on a small chip area. With the...
We propose a new methodology based on incremental logic restructuring for post-layout performance im...
In recent years the drive to produce more complex integrated circuits while spending less design tim...
[[abstract]]The authors propose a novel layout area model for quality measures in high-level synthes...
In recent years the drive to produce more complex integrated circuits while spending less design tim...
The problem of automatic layout synthesis is addressed. Given a description of the cell circuit to b...
Abstract. There are two ways to design a digital circuit. Covering methods are widely used which inc...
Computer-aided design of VLSI circuits is usually carried out in three synthesis steps: high-level s...
Traditionally, the common cost functions, the number of functional units, registers and selector inp...
While technology scaling has presented many new and exciting opportunities, new design challenges ha...
[[abstract]]As feature sizes shrink to deep sub-micron, the performance of VLSI chips becomes domina...
A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presen...
This paper presents the novel idea of multi-placement struc-tures, for a fast and optimized placemen...
This paper describes a method for incorporating layout parameters to better meet performance contrai...
International audienceThis paper presents a methodology for the synthesis of high performance analog...
As the technology advances, millions of transistors can be integrated on a small chip area. With the...
We propose a new methodology based on incremental logic restructuring for post-layout performance im...
In recent years the drive to produce more complex integrated circuits while spending less design tim...
[[abstract]]The authors propose a novel layout area model for quality measures in high-level synthes...
In recent years the drive to produce more complex integrated circuits while spending less design tim...
The problem of automatic layout synthesis is addressed. Given a description of the cell circuit to b...
Abstract. There are two ways to design a digital circuit. Covering methods are widely used which inc...
Computer-aided design of VLSI circuits is usually carried out in three synthesis steps: high-level s...
Traditionally, the common cost functions, the number of functional units, registers and selector inp...
While technology scaling has presented many new and exciting opportunities, new design challenges ha...
[[abstract]]As feature sizes shrink to deep sub-micron, the performance of VLSI chips becomes domina...
A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presen...
This paper presents the novel idea of multi-placement struc-tures, for a fast and optimized placemen...