Translating SpecCharts to VHDL

SpecCharts is a new language intended for system level specification and synthesis. It is based on hierarchical state diagrams and VHDL, and posseses many constructs designed to facilitate ease of description. Since current requirements demand that a specification language be simulatable, an approach for simulating SpecCharts needed to be developed. Rather than taking on the major task of writing a new simulator, a translator from SpecCharts to VHDL was implemented. This permits making use of the advantages that accompany the standardization of VHDL, including use of powerful compilers and simulators, while maintaining the ability to describe systems concisely and perform system level synthesis steps. The SpecChart to VHDL translator must convert each SpecChart abstraction to functionally equivalent VHDL. This report describes each of those abstractions and their VHDL implementation. The system takes as input a SpecChart and outputs a VHDL file which, when compiled, is a simulatable entity that can be used as any other VHDL entity. Several examples display how the translator can be used to verify SpecChart models of systems, thus adding to SpecCharts capability as a system level specification language