Traditionally, high-level synthesis (HLS) has been a fully automatic process over which the user has had little or no control. To make HLS an acceptable methodology for expert designers, we need to allow for more interactivity during synthesis. Since the scheduling step in HLS often determines the scope and quality of the ensuing synthesis tasks, we describe behavior-preserving transformations for manual rescheduling of behavior. We present the Structured Finite State Machine (SFSM) design model for scheduled behavior, show its equivalence to the behavioral Control-Data Flow Graph (CDFG), define primitive behavior-preserving transformations and indicate the utility of these transformations. The manual rescheduling capability we describe all...
The automated synthesis of a design from its behavioral description, known as high level synthesis, ...
We study a methodology for constructing scheduled systems by restricting successively the behavior o...
We present in this paper a novel control synthesis tech-nique for system-level specifications that a...
International audienceAs hardware designs get increasingly complex and time-to-market constraints ge...
The paper describes objectives of high-level synthesis. It concentrates on operation scheduling stra...
A central task in high-level synthesis isscheduling: the allocationof operations to clock cycles. Th...
A new heuristic scheduling algorithm for time constrained datpath synthesis is described. The algori...
Early scheduling algorithms usually adjusted the clock cycle duration to the execution time of the s...
This paper presents global high-level synthesis (HLS) approach which addresses the problem of synthe...
ISBN : 1-58113-937-3We introduce a new approach to take into account the memory architecture and the...
The objective of this work is to develop a new methodology for behavioural synthesis using a flow of...
A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. ...
The quality of high-level synthesis results for designs with complex and nested conditionals and l...
Complexities of applications implemented on embedded and programmable systems grow with the advances...
High level synthesis involves tasks that will transform an abstract or algorithmic level specificati...
The automated synthesis of a design from its behavioral description, known as high level synthesis, ...
We study a methodology for constructing scheduled systems by restricting successively the behavior o...
We present in this paper a novel control synthesis tech-nique for system-level specifications that a...
International audienceAs hardware designs get increasingly complex and time-to-market constraints ge...
The paper describes objectives of high-level synthesis. It concentrates on operation scheduling stra...
A central task in high-level synthesis isscheduling: the allocationof operations to clock cycles. Th...
A new heuristic scheduling algorithm for time constrained datpath synthesis is described. The algori...
Early scheduling algorithms usually adjusted the clock cycle duration to the execution time of the s...
This paper presents global high-level synthesis (HLS) approach which addresses the problem of synthe...
ISBN : 1-58113-937-3We introduce a new approach to take into account the memory architecture and the...
The objective of this work is to develop a new methodology for behavioural synthesis using a flow of...
A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. ...
The quality of high-level synthesis results for designs with complex and nested conditionals and l...
Complexities of applications implemented on embedded and programmable systems grow with the advances...
High level synthesis involves tasks that will transform an abstract or algorithmic level specificati...
The automated synthesis of a design from its behavioral description, known as high level synthesis, ...
We study a methodology for constructing scheduled systems by restricting successively the behavior o...
We present in this paper a novel control synthesis tech-nique for system-level specifications that a...