Architectural tradeoffs in synthesis of pipelined controls

Many high level synthesis systems produce designs without any consideration for the underlying architecture. In such systems, tradeoffs between area and delay can only be achieved by changing the synthesis constraints (e.g., number of functional units). These systems do not exploit the wider range of tradeoffs that can be achieved by modifying the underlying architecture. In this report we derive a relationship between architectural constraints and scheduling algorithms, and demonstrate how architectural styles impose certain restrictions on the scheduling process. In particular, we consider different control pipelining architectures. We also propose a versatile scheduling algorithm that is capable of synthesising designs for different control pipelining styles