Implementation and performance analysis of run time reconfiguration based on a field programmable gate array (FPGA) platform

This thesis focuses on the development and performance analysis of a Run Time Reconfigurable (RTR) system on the Xilinx Virtex 5 Field Programmable Gate Array (FPGA) platform. Due to the complexity and size of data encryption or decryption or compression algorithms, it is necessary to conserve hardware resources while maintaining flexibility of concurrently available algorithms. RTR is a technique that modifies a certain portion of the FPGA system by loading a partial configuration file at a run time without affecting the run time operations of the rest of the system. In this thesis, two different reconfigurable partitions are implemented: 1) a simple controller that controls the blinking frequency of the Light Emitting Diode (LED) indicator and serves as a proof-of-concept indicator for the RTR and 2) a suite of variant data encryption standards. Each partition can be dynamically reconfigured without interrupting the rest of the system execution. Different partial configuration files with variable sizes have been transmitted to the FPGA platform via a JTAG interface. The run time reconfigurable latency was measured for such partial configuration files. The performances of hardware resource utilization and power consumption in the RTR system were evaluated to validate the proposed implemented design