Advanced Relay Design and Technology for Energy-Efficient Electronics

As the era of traditional Complementary-Metal-Oxide-Semiconductor (CMOS) technology scaling is coming to an end, continual improvements in integrated-circuit (IC) performance and cost per function are becoming difficult to achieve without increasing power density. This necessitates the investigation of alternate device technologies that surmount the fundamental CMOS energy-efficiency limit and hence enable ultra-low-power ICs. To that end, a nano-electro-mechanical (NEM) relay technology is promising, because of its immeasurably low off-state leakage current and abrupt turn-on behavior, which provide for zero static power consumption and potentially very low dynamic power consumption.In this dissertation, relay design and process technology improvements, which led to the successful demonstration of relay-based digital IC building blocks, are discussed from both device- and circuit-level perspectives. A non-volatile (NV) memory relay design that can enable embedding of NV memory with relay-based logic circuits is also discussed. In addition, multielectrode relays that can lead to smarter design and compact implementation of zero-leakage digital integrated circuits are discussed