On-chip interconnect architectures : perspectives of layout, circuits, and systems

With exponentially increasing integration densities and shrinking characteristic geometries on a chip, the wires, rather than devices, become the dominant factor in deciding the performance, power consumption, and reliabilities of VLSI systems. Previous researches on interconnect centric design methodologies mainly concentrate on optimizing individual nets. Instead of searching for the best algorithm to optimize each individual net, we take a view of the on-chip interconnection architectures, and improve the system performance by considering both geometrical arrangements of wires, electrical behaviors of global distribution networks, as well as adopting innovative interconnect circuit styles. Traditional Manhattan routing restricts the wires on horizontal and vertical tracks. This artificial restriction causes excessive wirelength overhead over the Euclidean optimum and thus decreases the efficiency of the interconnect system. We investigated the optimal way to utilize the on-chip routing layers through non-Manhattan routing. We adopted multi-commodity flow models to measure the throughput of different on-chip interconnect architectures. Through careful analysis of the bottlenecks of the on-chip communication traffic, we found that the Y-architecture (3-directional routing) enjoys a lot of nice properties over other routing architectures. We developed a design methodology for Y- architecture, including power and clock distribution and a novel way to hide the via blockage effect.Clock distribution network is one of the most important interconnect on a chip. We studied the high speed clock distribution in the presence of parameter variations. We proposed a spectrum of solutions for circuits working at different frequencies: A variations aware clock tree synthesis algorithm for high-end ASICs, a multi-level mesh approach for microprocessors, and a transmission line network approach for future multi-giga hertz chips. Simulation results suggest that these approaches significantly improve clock distribution networks' resilience against process, voltage and temperature variations. We proposed a novel scheme to implement distortionless transmission lines for on-chip electrical signaling. By introducing intentional leakage conductance between the wires of a differential pair, the distortionless transmission line eliminates dispersion caused by the resistive nature of on-chip wires and achieves speed of light transmission. We show that it is feasible to construct distortionless transmission line with conventional silicon process. Simulation results show significant improvements in both speed and power consumption over conventional $RC$ wires with repeated buffer