Design Techniques for High-Frequency CMOS Integrated Circuits: From 10 GHz To 100 GHz

Technology developments have made CMOS a strong candidate in high-frequency applications because of its low power, low cost and higher-level integration. However, as an essential element in an RF building block, a CMOS device is not as good as a BJT device in terms of speed and a HEMT device in terms of noise performance. Therefore, conventional low-frequency design techniques for CMOS circuits may not satisfy the requirements for high-frequency applications wherein the operating frequencies get close to the cut-off frequency of a CMOS device. This research work explores design techniques for various high-frequency circuits at 10 GHz, 60 GHz and up to 110 GHz. Individual building blocks including low-noise amplifiers, voltage-controlled oscillators, high-frequency true-single-phase-clock frequency dividers, and mm-wave amplifiers are studied thoroughly using both theoretical analysis and practical circuit designs. Related fundamental techniques, such as MOS device modeling and de-embedding techniques, are also explored. Furthermore, as a prototype of system-level integration, a Ku-band LNB front-end is implemented for the application of a satellite receiver