The system-level design process typically involves refining a design specification down to the point where each of the system's components is described as a block diagram or netlist of abstract Register-Transfer (RT) level components. Although no standard set of RT components seems to exist across different design methodologies and backend technologies, on closer examination, we see that there indeed does seem to be a universally accepted set of RT-components that are used in the initial phase of design refinement, much before its implementation in a particular target technology. In this report, we describe the need for such a standard RT component set, describe such a parameterized library of standard (or generic) RT components, and evalua...
The use of VHDL as a hardware description language for automated synthesis has given rise to new pro...
This paper presents a system-level design environment for data transport processing systems. In this...
Includes bibliographical references.The increasing density in VLSI chips complicates the design as w...
The system-level design process typically involves refining a design specification down to the point...
The register transfer abstraction (RTL) has been estab-lished as the industrial standard for ASIC de...
Component generation is the task of mapping the abstract functional specification of register-transf...
The output of high-level synthesis typically consists of a netlist of generic RTL components and a s...
The importance of effective and efficient accounting of layout effects is well-established in High-L...
A new method of redesign for testability at the register-transfer level (RTL) is proposed. The metho...
High level synthesis is the process of generating register transfer (RT) level designs from behavior...
Existing heuristics and algorithms used in High-Level Synthesis typically assume a direct mapping of...
This paper presents a system-level design environment for data transport processing systems. In this...
Digital systems continue growing in complexity, but the design and verification productivity has not...
This paper describes a novel generator-generator language, LEGEND, for the defintion, generation and...
The importance of eective and ecient accounting of layout eects is well-established in High-Level Sy...
The use of VHDL as a hardware description language for automated synthesis has given rise to new pro...
This paper presents a system-level design environment for data transport processing systems. In this...
Includes bibliographical references.The increasing density in VLSI chips complicates the design as w...
The system-level design process typically involves refining a design specification down to the point...
The register transfer abstraction (RTL) has been estab-lished as the industrial standard for ASIC de...
Component generation is the task of mapping the abstract functional specification of register-transf...
The output of high-level synthesis typically consists of a netlist of generic RTL components and a s...
The importance of effective and efficient accounting of layout effects is well-established in High-L...
A new method of redesign for testability at the register-transfer level (RTL) is proposed. The metho...
High level synthesis is the process of generating register transfer (RT) level designs from behavior...
Existing heuristics and algorithms used in High-Level Synthesis typically assume a direct mapping of...
This paper presents a system-level design environment for data transport processing systems. In this...
Digital systems continue growing in complexity, but the design and verification productivity has not...
This paper describes a novel generator-generator language, LEGEND, for the defintion, generation and...
The importance of eective and ecient accounting of layout eects is well-established in High-Level Sy...
The use of VHDL as a hardware description language for automated synthesis has given rise to new pro...
This paper presents a system-level design environment for data transport processing systems. In this...
Includes bibliographical references.The increasing density in VLSI chips complicates the design as w...