Architectural tradeoff analysis of partitioned VLIWs

A Very Long Instruction Word (VLIW) processor is an architectural model that has been extensively adopted as computing paradigm in the field of Instruction Level Parallelism (ILP); a common design is based on a set of functional units, each able to issue an operation per cycle, connected to a shared register file.A VLIW has extreme requirements in terms of the number of gates, points of I/O, power dissipation and number of ports on its register file; characteristics that prevent implementation of the ideal architectural model on a single chip in current technologies, except for a limited number of functional units. A practical solution is to partition the architecture into multiple modules so as to meet technological constraints. The design of this brand of partitioned architectures requires an analysis of the overall effects of partitioning on both hardware and softwarer since the partitioning alters the performance in a non-intuitive manner.In this paper we investigate the tradeoffs involved in the design of partitioned VLIWs with a methodology that matches data obtained through software simulation with hardware estimation models, creating a global performance model. The focus of the analysis is to study the effects of multiple register files on the overall performance and on the area requirements of the processor modules