Traditional High-Level Synthesis (HLS) techniques do not allow reuse of complex, realistic datapath components during the tasks of scheduling and allocation. However, such datapath components are often custom designed and placed in technology libraries and databooks for potential reuse in future designs. We present a novel scheduling approach that, for the first time, permits reuse of such datapath components during HLS. Given a library of user-defined datapath components, an allocation of components from this library, and a limit on the maximum propagation delay through the datapath components, our algorithm generates an effective schedule for a given input behavior. We present experimental results of our approach on some HLS benchmarks us...
We present a robust datapath allocation method that is flexible enough to handle constraints imposed...
In high-level synthesis, scheduling maps operations into clock cycles. It can either be done at comp...
A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. ...
A new heuristic scheduling algorithm for time constrained datpath synthesis is described. The algori...
Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studi...
Complexities of applications implemented on embedded and programmable systems grow with the advances...
The choice of a clock period in designs with multicycle operations have a major influence on operato...
International audienceAs hardware designs get increasingly complex and time-to-market constraints ge...
The authors describe a new and efficient algorithm for concurrent scheduling, allocation and binding...
WOS: 000082431500001A multi-schedule data-path synthesis framework is described that is an improveme...
Dynamic loop scheduling, an algorithm that can efficiently schedule large, control-flow dominated de...
Modern VLSI designs get increasingly complex and time-to-market constraints get tighter. Using high ...
This paper presents a versatile scheduling model and an effi-cient control synthesis methodology whi...
In this paper, we propose an effective asynchronous datapath synthesis system to optimize statistica...
This paper presents a high-level test synthesis algorithm for operation scheduling and data path all...
We present a robust datapath allocation method that is flexible enough to handle constraints imposed...
In high-level synthesis, scheduling maps operations into clock cycles. It can either be done at comp...
A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. ...
A new heuristic scheduling algorithm for time constrained datpath synthesis is described. The algori...
Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studi...
Complexities of applications implemented on embedded and programmable systems grow with the advances...
The choice of a clock period in designs with multicycle operations have a major influence on operato...
International audienceAs hardware designs get increasingly complex and time-to-market constraints ge...
The authors describe a new and efficient algorithm for concurrent scheduling, allocation and binding...
WOS: 000082431500001A multi-schedule data-path synthesis framework is described that is an improveme...
Dynamic loop scheduling, an algorithm that can efficiently schedule large, control-flow dominated de...
Modern VLSI designs get increasingly complex and time-to-market constraints get tighter. Using high ...
This paper presents a versatile scheduling model and an effi-cient control synthesis methodology whi...
In this paper, we propose an effective asynchronous datapath synthesis system to optimize statistica...
This paper presents a high-level test synthesis algorithm for operation scheduling and data path all...
We present a robust datapath allocation method that is flexible enough to handle constraints imposed...
In high-level synthesis, scheduling maps operations into clock cycles. It can either be done at comp...
A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. ...