The system-level design process typically involves refining a design specification down to the point where each of the system's components is described as a block diagram or netlist of abstract Register-Transfer (RT) level components. In this report, we motivate the need for such a standard RT component set, and describe a library environment that supports automatic model generation, design reuse, and synthesis with technology-specific estimators. We demonstrate the efficacy of the standard RT-component set approach with experiments performed on the HLSW92 benchmarks. Our preliminary results indicate only a small overhead of about 10% in using these standard, generic components. We then describe an automatic model generation and technology ...
This paper presents a design environment for cycle-based systems, such as microprocessors, that perm...
The register transfer abstraction (RTL) has been estab-lished as the industrial standard for ASIC de...
This paper deals with the integration of an architectural synthesis tool within the existing CAD env...
The system-level design process typically involves refining a design specification down to the point...
An important benefit of high-level synthesis is rapid design space exploration through examination o...
High level synthesis is the process of generating register transfer (RT) level designs from behavior...
Component generation is the task of mapping the abstract functional specification of register-transf...
The importance of eective and ecient accounting of layout eects is well-established in High-Level Sy...
The output of high-level synthesis typically consists of a netlist of generic RTL components and a s...
Existing heuristics and algorithms used in High-Level Synthesis typically assume a direct mapping of...
The importance of effective and efficient accounting of layout effects is well-established in High-L...
High-level synthesis (HLS) has long relied on point models for RT-components that assume fixed area ...
To increase productivity in designing digital hardware components, high-level synthesis (HLS) is see...
This paper describes a novel generator-generator language, LEGEND, for the defintion, generation and...
High-level synthesis (HLS) tools greatly reduce the effort required in Register Transfer Level (RTL)...
This paper presents a design environment for cycle-based systems, such as microprocessors, that perm...
The register transfer abstraction (RTL) has been estab-lished as the industrial standard for ASIC de...
This paper deals with the integration of an architectural synthesis tool within the existing CAD env...
The system-level design process typically involves refining a design specification down to the point...
An important benefit of high-level synthesis is rapid design space exploration through examination o...
High level synthesis is the process of generating register transfer (RT) level designs from behavior...
Component generation is the task of mapping the abstract functional specification of register-transf...
The importance of eective and ecient accounting of layout eects is well-established in High-Level Sy...
The output of high-level synthesis typically consists of a netlist of generic RTL components and a s...
Existing heuristics and algorithms used in High-Level Synthesis typically assume a direct mapping of...
The importance of effective and efficient accounting of layout effects is well-established in High-L...
High-level synthesis (HLS) has long relied on point models for RT-components that assume fixed area ...
To increase productivity in designing digital hardware components, high-level synthesis (HLS) is see...
This paper describes a novel generator-generator language, LEGEND, for the defintion, generation and...
High-level synthesis (HLS) tools greatly reduce the effort required in Register Transfer Level (RTL)...
This paper presents a design environment for cycle-based systems, such as microprocessors, that perm...
The register transfer abstraction (RTL) has been estab-lished as the industrial standard for ASIC de...
This paper deals with the integration of an architectural synthesis tool within the existing CAD env...