Energy Efficient Integrated Circuits for Low Power Wireless Communication Applications

Low-power wireless receiver design has been an active area of research during thelast decade. One of the most difficult part of the design is generating a spectrally pureclock signal for demodulation in an energy efficient manner. The clock generation is usuallydone through either a phase-locked loop, and the energy cost of implementing a PLL isusually more power expensive than the the rest of the receiver. Therefore, the solutionsthus far have been to use a simple modulation schemes such as On-Off-Keying(OOk).However, such modulation schemes are spectrally inefficient, and as the density of wirelessdevices grow larger, more stringent spectral efficiency will be demanded even for low-powerxivapplications. This dissertation presents a search for an alternative to an envelope-detector.We have investigated a PLL-less coherent detection, as well as an ultra-low power PLLfor an alternative to an envelope detector. Chapter 1 describes the general link budgetrequired for such low-power applications. Popular low-power receiver architectures aredescribed in this chapter. Chapter 2 presents a PLL-less receiver architecture that employs asuper-regenerative oscillator as a phase storage element. The chapter details the system leveland circuit design as well as the measurement results. Chapter 3 presents a mathematicalmodel for super-regenerative reception of phase-modulated signal. The theoretical modelneeded to build the receiver presented in chapter 2 was not available at the time of the design.The authors investigated the behavior of super-regenerative receivers when it is used toreceive phase-modulated signals employing modulations such as phase-shift-keying (PSK).Chapter 4 describes a low-power PLL architecture that is promising enough to meet boththe power and the noise requirement of low-power wireless communication applicationsat 2.4 GHz. The in-band phase noise of sub-sampling PLL can approach the theoreticallimit of the reference phase noise. However, SSPLL can suffer from a significant spurioustone. This chapter presents a sub-sampling PLL architecture that can lower the spurioustone significantly without relying on a power-expensive calibration scheme. Furthermore,the entire loop (except the oscillator) consumes less than 500 microwatts of power, and thetotal power consumption of the PLL is less than 1 mW, suitable for low-power wirelesscommunication application