Phase-locked loops (PLLs) are critical components in modern electronics communication systems, where they are used to synthesize local oscillator signals for modulation and demodulation in wireless transceivers. They are also used to clock digital-to-analog converters (DACs), analog-to-digital converters (ADCs), and digital processors.Most PLLs incorporate either analog filters and voltage-controlled oscillators (VCOs) or digital filters and digitally-controlled oscillators (DCOs). The former are called analog PLLs and the latter are called digital PLLs. To date, analog PLLs have the best phase error performance, but digital PLLs have the lowest circuit area and are more compatible with highly-scaled CMOS IC technology. Thus, improving the ...
The advent of next-generation wireless standards demands ever-increasing data-rate communication sys...
2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24 - 27 May 201...
This brief presents a 1.9-GHz fractional-N digital phase-locked loop (DPLL) with a subexponent Delta...
ABSTRACT OF THE DISSERTATION A Time Amplifier Assisted FDC and DTC Linearization for Digital Fract...
Fractional-N phase-locked loop (PLL) frequency synthesizers are ubiquitous in modern communication s...
Graduation date: 2007A digital implementation of a PLL has several advantages compared to its\ud ana...
Abstract—Fractional- phase-locked loop frequency syn-thesizers based on time-to-digital converters (...
Digital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in the d...
The adoption of the digital/time converter (DTC) circuit in fractional-N phase-locked loops (PLLs) a...
Delta-sigma fractional-N phase-locked loops are used to generate high quality radio-frequency signal...
DoctorThis thesis presents several low-noise techniques for the design of fractional-N PLL, includin...
Digital PLLs (DPLLs) have emerged as reliable alternatives to analog PLLs since they are more robust...
One decade after their introduction into wireless applications, digital fractional-N phase-locked lo...
Circuit and system techniques for reducing phase noise in frequency synthesizers, and cancelling pha...
Fractional-N phase-locked loops (PLLs) are widely used to synthesize local oscillator signals for mo...
The advent of next-generation wireless standards demands ever-increasing data-rate communication sys...
2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24 - 27 May 201...
This brief presents a 1.9-GHz fractional-N digital phase-locked loop (DPLL) with a subexponent Delta...
ABSTRACT OF THE DISSERTATION A Time Amplifier Assisted FDC and DTC Linearization for Digital Fract...
Fractional-N phase-locked loop (PLL) frequency synthesizers are ubiquitous in modern communication s...
Graduation date: 2007A digital implementation of a PLL has several advantages compared to its\ud ana...
Abstract—Fractional- phase-locked loop frequency syn-thesizers based on time-to-digital converters (...
Digital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in the d...
The adoption of the digital/time converter (DTC) circuit in fractional-N phase-locked loops (PLLs) a...
Delta-sigma fractional-N phase-locked loops are used to generate high quality radio-frequency signal...
DoctorThis thesis presents several low-noise techniques for the design of fractional-N PLL, includin...
Digital PLLs (DPLLs) have emerged as reliable alternatives to analog PLLs since they are more robust...
One decade after their introduction into wireless applications, digital fractional-N phase-locked lo...
Circuit and system techniques for reducing phase noise in frequency synthesizers, and cancelling pha...
Fractional-N phase-locked loops (PLLs) are widely used to synthesize local oscillator signals for mo...
The advent of next-generation wireless standards demands ever-increasing data-rate communication sys...
2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24 - 27 May 201...
This brief presents a 1.9-GHz fractional-N digital phase-locked loop (DPLL) with a subexponent Delta...