Add to ORKGThis paper presents a novel statistical state-dependent timing model for voltage over scaled (VoS) logic circuits that accurately and rapidly finds the timing distribution of output bits. Using this model erroneous VoS circuits can be represented as error-free circuits combined with an error-injector. A case study of a two point DFT unit employing the proposed model is presented and compared to HSPICE circuit simulation. Results show an accurate match, with significant speedup gains. © 2014 IEEE
Current source based gate models achieve orders of mag-nitude of improved accuracy than the previous...
This paper proposes a novel approach to modeling of gate level timing errors during high-level instr...
Aggressive device scaling has made it imperative to account for process variations in the design flo...
This paper presents a novel statistical state-dependent timing model for voltage over scaled (VoS) l...
With the continued scaling of chip manufacturing technologies, the significance of process variation...
Abstract—To increase the accuracy of static timing analysis, the traditional nonlinear delay models ...
The purpose of this research is to develop a cost effective timing simulator for digital metal-oxide...
Abstract—Despite an increasing interest in digital sub-threshold circuits little research has been d...
Circuit designers typically combat variations in hardware and workload by increasing conservative gu...
Timing and electrical verification is an essential part of the design of VLSI digital MOS circuits. ...
This thesis describes the algorithms implemented in a new digital emitter-coupled logic (ECL) simula...
This paper describes a novel technique to analyze the effects of supply voltage noise on circuit del...
Variability in process parameters is making accurate timing anal-ysis of nano-scale integrated circu...
DoctorAggressive technology scaling in feature size has propelled designers to integrate millions of...
Abstract—To improve the accuracy of static timing analysis, the traditional nonlinear delay models a...
Current source based gate models achieve orders of mag-nitude of improved accuracy than the previous...
This paper proposes a novel approach to modeling of gate level timing errors during high-level instr...
Aggressive device scaling has made it imperative to account for process variations in the design flo...
This paper presents a novel statistical state-dependent timing model for voltage over scaled (VoS) l...
With the continued scaling of chip manufacturing technologies, the significance of process variation...
Abstract—To increase the accuracy of static timing analysis, the traditional nonlinear delay models ...
The purpose of this research is to develop a cost effective timing simulator for digital metal-oxide...
Abstract—Despite an increasing interest in digital sub-threshold circuits little research has been d...
Circuit designers typically combat variations in hardware and workload by increasing conservative gu...
Timing and electrical verification is an essential part of the design of VLSI digital MOS circuits. ...
This thesis describes the algorithms implemented in a new digital emitter-coupled logic (ECL) simula...
This paper describes a novel technique to analyze the effects of supply voltage noise on circuit del...
Variability in process parameters is making accurate timing anal-ysis of nano-scale integrated circu...
DoctorAggressive technology scaling in feature size has propelled designers to integrate millions of...
Abstract—To improve the accuracy of static timing analysis, the traditional nonlinear delay models a...
Current source based gate models achieve orders of mag-nitude of improved accuracy than the previous...
This paper proposes a novel approach to modeling of gate level timing errors during high-level instr...
Aggressive device scaling has made it imperative to account for process variations in the design flo...