In this session we show, in two case studies, how the roofline feature of Intel Advisor has been utilized to optimize the performance of kernels of the XGC1 and PICSAR codes in preparation for Intel Knights Landing architecture. The impact of the implemented optimizations and the benefits of using the automatic roofline feature of Intel Advisor to study performance of large applications will be presented. This demonstrates an effective optimization strategy that has enabled these science applications to achieve up to 4.6 times speed-up and prepare for future exascale architectures. # Goal/Relevance of Session The roofline model [1,2] is a powerful tool for analyzing the performance of applications with respect to the theoretical peak achiev...
There are many potential issues associated with deploying the Intel Xeon PhiTM (code named Knights L...
This article provides a comprehensive study of the impact of performance optimizations on the energy...
Manufacturers will likely offer multiple products with differing numbers of cores to cover multiple ...
The Roofline Performance Model is a visually intuitive method used to bound the sustained peak float...
The landscape of HPC architectures has undergone signi cant change in the last few years. Notably, t...
Three dimensional particle-in-cell laser-plasma simulation is an important area of computational phy...
One of the emerging architectures in HPC systems is Intel’s Knights Landing (KNL) many core chip, wh...
Tuning the performance of applications requires understanding the interactions between code and targ...
Manycores are consolidating in HPC community as a way of improving performance while keeping power e...
As we move towards exascale computing, the efficiency of application performance and energy utilizat...
International audienceThis work describes the challenges presented by porting parts of the gysela co...
This work describes the challenges presented by porting parts of the Gysela code to the In...
With energy-efficient architectures, including accelerators and many-core processors, gaining tracti...
James Reinders (Chief Evangelist of Intel® Software at Intel) and Jim Jeffers (Principal Engineer at...
Intel's Xeon Phi combines the parallel processing power of a many-core accelerator with the programm...
There are many potential issues associated with deploying the Intel Xeon PhiTM (code named Knights L...
This article provides a comprehensive study of the impact of performance optimizations on the energy...
Manufacturers will likely offer multiple products with differing numbers of cores to cover multiple ...
The Roofline Performance Model is a visually intuitive method used to bound the sustained peak float...
The landscape of HPC architectures has undergone signi cant change in the last few years. Notably, t...
Three dimensional particle-in-cell laser-plasma simulation is an important area of computational phy...
One of the emerging architectures in HPC systems is Intel’s Knights Landing (KNL) many core chip, wh...
Tuning the performance of applications requires understanding the interactions between code and targ...
Manycores are consolidating in HPC community as a way of improving performance while keeping power e...
As we move towards exascale computing, the efficiency of application performance and energy utilizat...
International audienceThis work describes the challenges presented by porting parts of the gysela co...
This work describes the challenges presented by porting parts of the Gysela code to the In...
With energy-efficient architectures, including accelerators and many-core processors, gaining tracti...
James Reinders (Chief Evangelist of Intel® Software at Intel) and Jim Jeffers (Principal Engineer at...
Intel's Xeon Phi combines the parallel processing power of a many-core accelerator with the programm...
There are many potential issues associated with deploying the Intel Xeon PhiTM (code named Knights L...
This article provides a comprehensive study of the impact of performance optimizations on the energy...
Manufacturers will likely offer multiple products with differing numbers of cores to cover multiple ...