Energy-Efficient High-Performance CMOS VLSI Design for Electronic-Photonic Integration and Biological Applications

Data analysis, storage and communication has become a very important subject for research nowadays. Due to higher demand for data, power and area reduction have drawn more attention in recent research. In this dissertation we propose new system for data communication through optical links which is area and power efficient while maintaining high performance. We also propose a new approach for biosensing which also focuses on area and power efficiency with improved performance which enables analyzing huge amounts of data.In the first part of this dissertation, a 1Tb/s transceiver system is introduced. This system is designed for microring resonator links. Therefore, a control loop design is also introduced in this part for wavelength locking. Two versions of the 1Tb/s transceiver with less than 90fJ/bit energy efficiency is implemented in 22nm FDSOI to achieve 5Tbit/(mm2) and 0.8Tbit/(mm2) densities. New system and circuit designs are proposed to achieve such low power and density at 1Tb/s. A closed loop wavelength locking control loop is also proposed consuming low power and area while locking the rings in less than 25µs. A 20 channel wavelength locking system is implemented in TSMC 65nm. In the second part of this dissertation, we introduce biological sensors and sensor interfaces for biological applications. Nanopore sensors enable a wide range of sensors from DNA sequencing to polymer mass spectrometry by exploiting the resistive pulse technique. The small and high-speed sensor signal can make the electronics design challenging. The designer is often faced with a bewildering choice of architectures and circuit topologies. In this part, we review the most prominent circuits and architectures used in nanopore sensing highlighting the advantages and disadvantages of each approach. Additionally, noise analysis and SNR calculations are shown for each topology. We also provide a graphical method to allow the designer to narrow down their choice for a given set of requirements. As the need for large sensor arrays is continually increasing, we discuss the different approaches to scaling the system when using an array of sensors. We also introduce the system design of a new high precision potentiostat. Our direct current-to-digital conversion is capable of sensing picoampere (pA) currents without a need for transimpedance amplifiers (TIAs). Our idea utilizes a ∆Σ modulator with one very important difference, current feedback via slope scaling. This feature allows us to utilize noiseless elements such as capacitors in the feedback loop to achieve high performance. We have validated the system using both theory and experiment. Performance improvement over current systems is first demonstrated by performing a theoretical analysis of the expected noise of the system. A 10×10 cm2 PCB prototype was fabricated as a proof of concept. The slope scaling idea is applied to both first and second order ∆Σ Analog to Digital Converters (ADCs) with signal input bandwidth of 1.57 KHz with an oversampling ratio of 64. Signal-to-Noise-and-Distortion Ratio (SNDR) of 40 dB and 60 dB is achieved with 1st and 2nd order ∆Σ ADCs, respectively. The noise floor of the implemented circuit is 569 fA over a 1KHz bandwidth and was tested for input currents ranging from 100 pA to 1 µA. In this part, we also propose a direct current to digital 125µW, area efficient (0.042mm2) 81dB DR, 8KS/s current sensing ADC implemented in 45nm CMOS capable of sensing sub-pA currents. Our approach combines the TIA and ADC into a unified structure by folding a low-noise capacitive TIA into the first stage integrator of a 2nd order Delta-Sigma (∆Σ) modulator. We mitigate the common issue of feedback DAC noise faced by current sensing ∆Σ converters by using a low-noise current scaling technique. In our approach an integrator-differentiator pair scales the DAC feedback current using capacitors. Since the DAC is current based the integrator is simply a charge-pump, alleviating the bandwidth issues arising from the periodic reset required by the integrator. However, the periodic reset forces the converter to operate in an incremental mode lowering the dynamic range of the converter. We overcome this by using a floating correlated double sampling (CDS) technique. The correlated double sampling also enables the use of single stage common source amplifiers while achieving a high-gain resulting in a low-power area-efficient design