reliability analysis of gate-all-around floating gate (GAA-FG) with variable oxide thickness for flash memory cell

In this work, a concept of tunnel barrier engineering using Variable Oxide Thickness (VARIOT) of low-k/high-k stack is implemented in Gate-All-Around Floating Gate (GAA-FG) memory cell to reduce P/E operational voltage, improve the efficiency of data retention after 10 years and endurance after 10 4 of P/E cycles. This work begins with the VARIOT optimization of five high-k dielectric materials which are ZrO 2 , HfO 2 , La 2 O 3 , Y 2 O 3 and Al 2 O 3 in which these high-k dielectrics can be embedded onto low-k dielectric layer which is SiO 2 . The impact of the proposed structure on the device characteristic is analyzed through simulated transient performances of the GAA-FG memory cell with optimized parameters are accessed to offset the trade-off between P/E characteristics and the device reliability including data retention and endurance