Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs

The design of secure circuits in emerging technologies is an appealing area that requires new efforts and attention as an effective solution to secure applications with power constraints. The paper deals with the optimized design of DPA-resilient hiding-based techniques, using Tunnel Field-Effect Transistors (TFETs). Specifically, proposed TFET implementations of Dual-Precharge-Logic primitives optimizing their computation tree in three different ways, are applied to the design of PRIDE Sbox-4, the most vulnerable block of the PRIDE lightweight cipher. The performance of simulation-based DPA attacks on the proposals have shown spectacular results in security gain (34 out of 48 attacks fail for optimized computation trees in TFET technology) and power reduction (x25), compared to their CMOS-based counterparts in 65nm, which is a significant advance in the development of secure circuits with TFETs.Ministerio de Economía y Competitividad TEC2017-87052-PMinisterio de Economía y Competitividad PID2020-116664RB-I00Junta de Andalucía Projectos US-1380876 y US-1380823European Union’s Horizon 2020 Grant Agreement No. 95262 and No. 80447