FPGA Implementation of Robot Obstacle Avoidance Controller based on Enzymatic Numerical P Systems

It is a long-cherished wish to implement numerical P systems (NPS) on a parallel architecture so that its large scale parallelism can be exploited to speedup computation tremendously. FPGA is a reconfigurable hardware in which operations are triggered so synchronized by edge or level of activating signals, making it an eligible platform to implement NPS and its variant, enzymatic numerical P system (ENPS). In this article, a NPS and a ENPS designed as robot controllers are implemented in FPGA, achieving a speedup of 105 comparing to software simulation. FPGA hardened NPS in this research can be regarded as a heterogeneous multicore processor since membranes inside work as processing units which possess different functions. FPGA hardened NPS is imparted universal asynchronous receiver/transmitter (UART) communication ability to push it closer to real-life application. FPGA hardened ENPS consume less hardware resources and power for less complicate membrane structures and processes