Statistical design of MOS VLSI circuits with designed experiments

Many methods for the statistical design and analysis of integrated circuits have been proposed over the past years. However, these methods typically require a large number of computationally expensive circuit simulator runs, and their applications are limited to small circuits.This research investigated new approaches for the statistical design and analysis of MOS integrated circuits. This work has resulted in a new and efficient circuit performance modeling approach to statistical design. The proposed approach approximates the circuit performances, such as gain and delay, by fitted models of the inputs to the circuit simulator. The computationally inexpensive fitted models are then used as surrogates of the circuit simulator to predict and optimize the parametric yield and to achieve off-line quality control. The use of statistical design and analysis of experiments for model construction have been investigated theoretically and experimentally, and different methods to assess the adequacy of a fitted performance model have been studied.U of I OnlyETDs are only available to UIUC Users without author permissio