Add to ORKGReconfigurable chips can be used to enhance the yield of chip production. These chips contain redundant elements that can be used to replace the defective elements. The fault covering problem is to assign the redundant elements to the defective elements such that the chip will function properly. We studied fault covering problems on special architectures, Random Access Memories and Programmable Logic Arrays, and developed a general formulation and algorithm for solving fault covering problems on a large class of reconfigurable chips.U of I OnlyETDs are only available to UIUC Users without author permissio
As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tou...
As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tou...
Abstract: Redundancy based hardening techniques are applied at the pre-synthesis or synthesis level....
Reconfigurable chips are fabricated with redundant elements that can be used to replace the faulty e...
The ever-shrinking technology features have as a direct consequence the increase of defect density i...
150 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1993.Advances in VLSI (Very Large ...
This thesis examines three specific issues of defect-tolerant VLSI: (1) design and reconfiguration o...
In large VLSI/WSI arrays, improved reliability and yield can be obtained through reconfiguration tec...
International audienceReliability and other uncertainty issues are serious problems for Field Progra...
Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to ...
Reconfigurable hardware can be employed to tolerate permanent faults. Hardware components comprising...
As field programmable gate arrays find increasing use in aerospace and terrestrial applications, a n...
With the steady increase of transistor counts and the increase of wafer sizes, design for manufactur...
Scaling of transistor's channel length is entering the realm of atomic and molecular geometries maki...
Summarization: SRAM-based FPGAs are susceptible to SingleEvent Upsets (SEUs) in radiation-exposed en...
As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tou...
As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tou...
Abstract: Redundancy based hardening techniques are applied at the pre-synthesis or synthesis level....
Reconfigurable chips are fabricated with redundant elements that can be used to replace the faulty e...
The ever-shrinking technology features have as a direct consequence the increase of defect density i...
150 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1993.Advances in VLSI (Very Large ...
This thesis examines three specific issues of defect-tolerant VLSI: (1) design and reconfiguration o...
In large VLSI/WSI arrays, improved reliability and yield can be obtained through reconfiguration tec...
International audienceReliability and other uncertainty issues are serious problems for Field Progra...
Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to ...
Reconfigurable hardware can be employed to tolerate permanent faults. Hardware components comprising...
As field programmable gate arrays find increasing use in aerospace and terrestrial applications, a n...
With the steady increase of transistor counts and the increase of wafer sizes, design for manufactur...
Scaling of transistor's channel length is entering the realm of atomic and molecular geometries maki...
Summarization: SRAM-based FPGAs are susceptible to SingleEvent Upsets (SEUs) in radiation-exposed en...
As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tou...
As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tou...
Abstract: Redundancy based hardening techniques are applied at the pre-synthesis or synthesis level....