Techniques for automatic test knowledge extraction from compiled circuits

In the past, research has shown that the use of high-level test knowledge can be used to greatly accelerate the test generation process. The problem was that no techniques were developed to extract this knowledge from a circuit. Typically, the only solution for a circuit designer was to manually extract the test knowledge. When designers are using sophisticated high-level synthesis tools (e.g., a silicon compiler), the designer may not be competent to extract this type of knowledge. In this thesis, solutions to the problem of automatically extracting this high-level knowledge from the structure of a compiled circuit are presented.Two different types of knowledge are addressed. The first type of knowledge is a testability measure. We present solutions to the problem estimating the testability for circuits defined at a functional level. By using an information theoretic testability measure, the concepts of controllability and observability are captured. Instead of requiring exhaustive enumeration of the input space to compute the measure (as has been previously suggested), we presented two different methods for efficiently and accurately estimating the measure. In addition, we have present various applications of the measure, including automatic circuit partitioning and test point insertion.The second type of knowledge is used in test generation. We describe techniques to automatically extract high-level test and DFT knowledge from the structure of compiled circuits. These techniques work autonomously and require no user intervention. This system has been implemented in a SUN workstation environment and is known as DELPHI. It operates on the high-level dataflow representation of a compiled circuit and generates the test knowledge in the form of lists of primary input assignments. Achieving both high levels of fault coverage and fast performance, DELPHI can extract test knowledge from both non-sequential and sequential circuits. When test knowledge extraction is unsuccessful, additional DFT knowledge is obtained to efficiently represent design for testability options. In those cases in which users are able to provide test knowledge, techniques to verify user-provided knowledge are described.U of I OnlyETDs are only available to UIUC Users without author permissio