This thesis consists of two parts. In the first part, we have discussed a multilevel network synthesis system, SYLON-XTRANS, which is an extension of the original Transduction method. In Chapter 1, we have discussed how to represent MSPF and CSPF by the use of sum-of-product form. Because of the use of the sum-of-product form, SYLON-XTRANS can handle a network with a larger number of input variables than the original Transduction method. We have discussed the calculation of MSPF and CSPF in a network with a mixture of simple gates of different types, whereas MSPF and CSPF were defined for NOR gates only in the original Transduction method. In Chapter 2, we have discussed a new procedure, SYLON-XTRANS-INI, for synthesizing an initial network...
Within the field of automated logic design, the optimal synthesis of combinational logic has remaine...
[[abstract]]In this paper, we present logic optimization techniques for multilevel combinational net...
Abstract—A new algorithm for obtaining efficient architectures composed of threshold gates that impl...
This thesis consists of two parts. In the first part, we have discussed a multilevel network synthes...
As VLSI integration size and chip complexity keep increasing, logic design is becoming more complex ...
The logic networks that can be put on a single chip continues to grow in size and complexity. There ...
Many efficient ways for two-level logic minimization of Boolean functions have been presented. They ...
In this chapter we will provide a rigorous survey of the basics of modern multi-level logic synthesi...
Abstract — In this paper we present a TL specific synthesis tool that aims to exploit the specific c...
With the increased complexity of Very Large Scaled Integrated (VLSI) circuits, multilevellogic synth...
The purpose of this investigation has been to implement, in the form of computer programs, two algor...
The traditional approaches for multilevel logic optimization involve representing Boolean functions ...
In this thesis, new algorithms for logic synthesis areexplored. Our work is motivated by two observa...
217 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.In the optimization phase, th...
In this paper an evolutionary technique for synthesizing Multi-Valued Logic (MVL) functions using Ne...
Within the field of automated logic design, the optimal synthesis of combinational logic has remaine...
[[abstract]]In this paper, we present logic optimization techniques for multilevel combinational net...
Abstract—A new algorithm for obtaining efficient architectures composed of threshold gates that impl...
This thesis consists of two parts. In the first part, we have discussed a multilevel network synthes...
As VLSI integration size and chip complexity keep increasing, logic design is becoming more complex ...
The logic networks that can be put on a single chip continues to grow in size and complexity. There ...
Many efficient ways for two-level logic minimization of Boolean functions have been presented. They ...
In this chapter we will provide a rigorous survey of the basics of modern multi-level logic synthesi...
Abstract — In this paper we present a TL specific synthesis tool that aims to exploit the specific c...
With the increased complexity of Very Large Scaled Integrated (VLSI) circuits, multilevellogic synth...
The purpose of this investigation has been to implement, in the form of computer programs, two algor...
The traditional approaches for multilevel logic optimization involve representing Boolean functions ...
In this thesis, new algorithms for logic synthesis areexplored. Our work is motivated by two observa...
217 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.In the optimization phase, th...
In this paper an evolutionary technique for synthesizing Multi-Valued Logic (MVL) functions using Ne...
Within the field of automated logic design, the optimal synthesis of combinational logic has remaine...
[[abstract]]In this paper, we present logic optimization techniques for multilevel combinational net...
Abstract—A new algorithm for obtaining efficient architectures composed of threshold gates that impl...