Edge-contact MoS2 transistors made by thermal scanning probe lithography

Two-dimensional materials (2DM) have emerged as potential candidates for low power electronics, optoelectronics, and sensing [1]. However, the chemical and physical processes involved in conventional lithography methods, have shown detrimental effects on 2DM devices [2,3]. Another bottleneck in the fabrication of 2DM devices is its contact resistance to metals. The characteristic Schottky barrier appearing at the junction between a 2DM and a 3D metallic contact remains a limiting factor in the performance of 2DM-based electronic devices. When 2DM are exposed to air, molecules adhere to the surface forming layers with a thickness that can be of the same order of the 2DM itself, affecting the 2DM-metal interface in top-contact devices. Besides, due to the inertness of the basal planes in 2DM, top contacts can only be achieved through Van der Waals forces. When multilayered systems are considered, this becomes an even bigger issue due to the large conductivity anisotropy of 2DM between in- and out-of-plane directions. On the other hand, edge-contacted devices enable shorter bonding distances and covalent bonding to every layer but at the expense of a more complex fabrication process [4]. Here, we propose a process based on thermal scanning probe lithography (t-SPL) to fabricate edge-contact 2DM transistors (see Fig. 1). It has already been demonstrated that t-SPL is a better candidate than electron beam lithography for the fabrication of top-contact 2DM-based transistors as the use of electrons is avoided and the heat from the tip remains sufficiently far from the 2DM to avoid the deterioration of the 2DM properties [3]. Here, we go one-step further and achieve edge-contact by combining t-SPL with ion-milling and physical vapor deposition (PVD) in the same chamber [5], achieving a clean edge contact. The proposed process is schematically shown in Fig. 1a and carried-out as follows. MoS2 flakes are mechanically exfoliated onto Si substrates covered by a 200 nm SiO2 layer. For the fabrication of the contacts, a bilayer of PPA (30 nm)-PMGI (90 nm) is used. Patterning is performed by a mix-and-match approach combining t-SPL for the small features and direct laser writing for large features, both implemented using the same commercial apparatus. After wet etch in TMAH solution, the samples are placed into the PVD chamber where Ar+ milling is used to etch the flakes and, subsequently, the deposition of Cr-Au or Ti-Au is performed by thermal evaporation without breaking the vacuum. After the final lift-off, clean edge-contacts are obtained. Devices with different 2DM thicknesses are fabricated. The electrical characterization shows that multilayered devices achieve better performances with respect to single layer devices, with on/off ratios of up to 108 and mobilities up to 70 cm2V-1s-1. These values are comparable with the highest reported values for MoS2 transistors without hBN encapsulation. Low-temperature measurements down to 80 K are performed and used to extract the Schottky barrier height finding values down to 68 meV. For the sake of comparison, top-contact devices are also fabricated following a similar process but without ion milling. Top-contact devices show poorer performance compared to edge-contact ones with mobilities below 5 cm2V-1s-1 and a highest on/off ratio of 106, most likely due to surface contamination. [1] S. Das et al., Annu. Rev. Mater. Res. 45 (2015) 1–27. [2] Z. Cheng et al., 2D Mater. 6 (2019) 034005. [3] X. Zheng et al., Nat. Electron. 2 (2019) 17–25. [4] Y. Matsuda et al., J. Phys. Chem. C. 114 (2010) 17845–17850. [5] Z. Cheng et al., Nano Lett. 19 (2019) 5077–5085